Loss of signal detection for high-speed serial links
In one embodiment, a loss-of-signal detector is provided that is immune to variations in common mode voltage for a received differential input signal. The loss-of-signal detector is configured is to use a reference voltage that depends upon the common mode voltage.
1. A circuit, comprising:
a loss-of-signal detector configured to compare a pair of differential input voltages having a common mode voltage to a reference voltage that depends upon the common mode voltage; and
a differential amplifier configured to control a current through a variable resistor to produce the reference voltage at a first terminal of the variable resistor and to produce the common mode voltage at an opposing second terminal of the variable resistor,
wherein the loss-of-signal detector includes:
a pre-amplifier configured to amplify the differential input voltages into amplified differential input voltages;
a first comparator configured to compare a first one of the amplified differential voltages to the reference voltage to provide a first compared voltage;
a second comparator configured to compare a second one of the amplified differential voltages to the reference voltage to provide a second compared voltage; and
an OR gate configured to logically OR the first and second compared voltages to provide a first loss-of-signal voltage (Vlos 1 ).
2. The circuit of claim 1 , wherein the loss-of-signal detector further includes a peak detector circuit configured to detect a peak in Vlos 1 to provide a peak-detected signal, and wherein the loss-of-signal detector further includes a third comparator configured to compare the peak-detected signal to a threshold voltage to provide a second loss-of-signal voltage (Vlos 2 ).
3. The circuit of claim 2 , wherein the loss-of-signal detector further includes a multiplexer configured to select between Vlos 1 and Vlos 2 to provide a multiplexer output signal, and wherein the loss-of-signal detector further includes an inverter configured to invert the multiplexer output signal into a final loss-of-signal voltage (Vlos).
4. A circuit, comprising:
a loss-of-signal detector configured to compare a pair of differential input voltages having a common mode voltage to a reference voltage that depends upon the common mode voltage;
a differential amplifier configured to control a current through a variable resistor to produce the reference voltage at a first terminal of the variable resistor and to produce the common mode voltage at an opposing second terminal of the variable resistor; and
a differential input receiver configured to receive a differential input signal received at a pair of first resistors, and a pair of capacitors coupled to the pair of first resistors and configured to provide the differential input voltages, and wherein the loss-of-signal detector is configured to receive the differential input voltages through a pair of second resistors, the second resistors having a resistance that is larger than a resistance for the first resistors.
5. The circuit of claim 1 , wherein the pre-amplifier is a common-gate amplifier.
6. The circuit of claim 5 , wherein the common-gate amplifier includes a pair of current sources.
7. The circuit of claim 1 , wherein the differential amplifier is configured to control the current by driving a gate of a transistor.
8. The circuit of claim 2 , wherein the peak detector includes an integrating circuit.
9. A method, comprising:
driving a current through a series of resistors to produce a reference voltage and a first common mode voltage;
deriving a pair of first differential input voltages from a received differential input signal such that a common mode voltage for the pair of first differential input voltages is the first common mode voltage;
comparing the pair of first differential input voltages to the reference voltage to produce a loss-of-signal voltage (Vlos);
receiving the differential input signal through a pair of first resistors to produce a pair of second differential input voltages; and
blocking a DC-voltage in the pair of second differential input voltages to produce a pair of third differential input voltages,
wherein the deriving the pair of first differential input voltages comprises receiving the pair of third differential input voltages through a pair of second resistor.
10. The method of claim 9 , wherein comparing the pair of first differential input voltages comprises amplifying the pair of first differential input voltages into a pair of amplified differential input voltages and comparing each of the amplified differential input voltages to the reference voltage to produce a first signal detection voltage.
11. The method of claim 10 , further comprising peak detecting the first signal detection voltage to produce a peak-detected signal and comparing the peak-detected signal to produce a second signal detection voltage.
12. The method of claim 11 , further comprising selecting between the first and second signal detection voltages to produce a selected signal and inverting the selected signal to produce Vlos.
13. The circuit of claim 4 , wherein the loss-of-signal detector comprises a peak detector circuit configured to detect a peak in Vlos 1 to provide a peak-detected signal, and wherein the loss-of-signal detector further includes a third comparator configured to compare the peak-detected signal to a threshold voltage to provide a second loss-of-signal voltage (Vlos 2 ).
14. The circuit of claim 4 , wherein the loss-of-signal detector comprises a multiplexer configured to select between Vlos 1 and Vlos 2 to provide a multiplexer output signal, and wherein the loss-of-signal detector further includes an inverter configured to invert the multiplexer output signal into a final loss-of-signal voltage (Vlos).