Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
View Patent ↗In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.
1. An article of manufacture comprising a first interconnection array configured to mate with a corresponding second interconnection array, the first interconnection array comprising: an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch; an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch, wherein: the outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least the specified pitch, wherein the depopulated rectangular ring has no connectors; the outer rectangular ring has a plurality of empty locations having no connectors; and the plurality of empty locations includes at least one depopulated set of locations having no connectors that extends from the depopulated rectangular ring to an outer edge of the interconnection array, wherein: each connector of the inner sub-array is a power connector configured to carry a power supply voltage; and the outer rectangular ring comprises: one or more signal connectors, each configured to carry a signal; and one or more power connectors, each configured to carry a power supply voltage.
2. The article of claim 1 , wherein:
the first interconnection array is a ball grid array of a packaged semiconductor device; and
the second interconnection array is a landing pad array of a printed circuit board.
3. The article of claim 2 , wherein the article comprises the packaged semiconductor device.
4. The article of claim 3 , wherein the article further comprises the printed circuit board mated with the packaged semiconductor device.
5. The article of claim 1 , wherein:
the first interconnection array is a landing pad array of a printed circuit board; and
the second interconnection array is a ball grid array of a packaged semiconductor device.
6. The article of claim 5 , wherein the article comprises the printed circuit board.
7. The article of claim 5 , wherein:
the printed circuit board comprises a plurality of layers; and
each landing pad in the landing pad array is connected to a corresponding via that extends to all of the layers in the printed circuit board.
8. The article of claim 7 , wherein two or more SerDes channels and two or more DQS groups of signals are routed in a single layer of the printed circuit board.
9. The article of claim 7 , wherein:
the inner sub-array of locations is fully populated; and
each landing pad in the fully populated, inner sub-array of locations and the corresponding via in the printed circuit board function as a heat sink for a corresponding ball in the ball grid array.
10. The article of claim 1 , wherein the depopulated rectangular ring has a width of at least twice the specified pitch.
11. The article of claim 1 , wherein two or more depopulated sets of locations extend from the depopulated rectangular ring to the outer edge of the interconnection array, thereby dividing the outer rectangular ring into a plurality of contiguous sets of connectors.
12. The article of claim 1 , wherein the inner sub-array has no empty locations.