Configuration of selected modules of a hardware block within a programmable logic device

1. A method comprising:

receiving in a computer system configuration information for a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD), wherein the configuration information is received from a user of the computer system;

generating in the computer system a plurality of models for the plurality of hardware modules, wherein a generated model includes the configuration information received for a hardware module; and

merging in the computer system the generated models into a combined model of the hardware block, wherein the combined model includes the configuration information received for the plurality of hardware modules and interconnections specified between the plurality of hardware modules.

2. The method of claim 1 , wherein at least one of the generated models includes the configuration information for a subset of hardware modules of the hardware block.

3. The method of claim 2 , wherein the subset includes a single hardware module of the hardware block.

4. The method of claim 1 , wherein each generated model is a single level hardware description language (HDL) model.

5. The method of claim 1 , wherein:

the generated model for a first one of the hardware modules includes a connection between the first hardware module and a signal path of the hardware block;

the generated model for a second one of the hardware modules includes a connection between the second hardware module and the signal path; and

the combined model specifies the interconnection between the first and second hardware modules using the connections of both the first and second hardware modules to the signal path.

6. The method of claim 1 , wherein the hardware block is adapted to pass signals between programmable logic blocks of the PLD and external ports of the PLD.

7. The method of claim 1 , wherein the hardware block comprises:

a serializer/deserializer (SERDES) hardware module;

a physical coding sublayer (PCS) hardware module; and

a hard intellectual property core (IP) hardware module.

8. The method of claim 1 , further comprising displaying a set of hardware modules to the user in a graphical user interface, wherein the displayed set of hardware modules has a one-to-one correspondence with the hardware modules of the hardware block.

9. The method of claim 1 , further comprising generating configuration data based on the combined model, wherein the configuration data is adapted to be programmed into the PLD to configure the PLD for operation.

10. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a method comprising:

receiving configuration information for a plurality of hardware modules of an embedded hardware block of a programmable logic device (PLD), wherein the configuration information is received from a user of the system,

generating a plurality of models for the plurality of hardware modules, wherein a generated model includes the configuration information received for a hardware module; and

merging the generated models into a combined model of the hardware block, wherein the combined model includes the configuration information received for the plurality of hardware modules and interconnections specified between the plurality of hardware modules.

11. The system of claim 10 , wherein at least one of the generated models includes the configuration information for a subset of hardware modules of the hardware block.

12. The system of claim 11 , wherein the subset includes a single hardware module of the hardware block.

13. The system of claim 10 , wherein each generated model is a single level hardware description language (HDL) model.

14. The system of claim 10 , wherein:

the generated model for a first one of the hardware modules includes a connection between the first hardware module and a signal path of the hardware block;

the generated model for a second one of the hardware modules includes a connection between the second hardware module and the signal path; and

the combined model specifies the interconnection between the first and second hardware modules using the connections of both the first and second hardware modules to the signal path.

15. The system of claim 10 , wherein the hardware block is adapted to pass signals between programmable logic blocks of the PLD and external ports of the PLD.

16. The system of claim 10 , wherein the hardware block comprises:

a serializer/deserializer (SERDES) hardware module;

a physical coding sublayer (PCS) hardware module; and

a hard intellectual property core (IP) hardware module.

17. The system of claim 10 , wherein the hardware modules are substantially co-located in a region of the PLD.

18. The system of claim 10 , wherein the method further comprises displaying a set of hardware modules to the user in a graphical user interface, wherein the displayed set of hardware modules has a one-to-one correspondence with the hardware modules of the hardware block.

19. The system of claim 10 , wherein the method further comprises generating configuration data based on the combined model, wherein the configuration data is adapted to be programmed into the PLD to configure the PLD for operation.

20. A programmable logic device (PLD) comprising:

an embedded hardware block including a plurality of hardware modules, wherein:

each hardware module can be represented by a model generated by a computer system based on configuration information received for the hardware module; and

the generated models can be merged in the computer system into a combined model of the hardware block, wherein the combined model includes the configuration information received for the plurality of hardware modules and interconnections specified between the plurality of hardware modules.