IP Library Granted Patent US 9,152,756
Granted Patent B2
US 9,152,756 · App. 14/137,443 · Granted Oct 6, 2015

Group based routing in programmable logic device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,152,756
App. No.
14/137,443
Granted
Oct 6, 2015
Kind
B2
Abstract

Various techniques are provided to route connections within a programmable logic device (PLD). In one example, a method includes determining timing slacks for connections described in a netlist for a programmable logic device (PLD). The method also includes determining a plurality of priority groups. The connections are associated with one or more of the priority groups based on the timing slacks. The method also includes routing the connections associated with each priority group, from a highest priority group to a lowest priority group. Each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed. Additional methods, systems, machine-readable mediums, and other techniques are also provided.

Claims (35)

1. A computer-implemented method comprising:

determining timing slacks for connections described in a netlist for a programmable logic device (PLD);

determining a plurality of priority groups, wherein the connections are associated with one or more of the priority groups based on the timing slacks; and

routing the connections, for PLD configuration, associated with each priority group, from a highest priority group to a lowest priority group, wherein each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed, the iterative routing of each priority group comprising updating the timing slacks corresponding to routed connections; and adjusting at least one of the plurality of priority groups based on the updated timing slacks.

2. The computer-implemented method of claim 1 , wherein the iterative routing for at least one of the plurality of priority groups further comprises connection-based routing negotiation.

3. The computer-implemented method of claim 1 , wherein the plurality of priority groups are determined by percentages applied to a range of the timing slacks.

4. The computer-implemented method of claim 1 , wherein the plurality of priority groups are determined by percentages applied to a total number of the connections.

5. The computer-implemented method of claim 1 , wherein the lowest priority group includes all the connections.

6. The computer-implemented method of claim 1 , wherein the determining timing slacks comprises determining positions of source and load nodes for the connections.

7. The computer-implemented method of claim 1 , wherein the determining timing slacks comprises estimating signal propagation times between source and load nodes for the connections.

8. A computer-implemented method comprising:

determining timing slacks for connections described in a netlist for a programmable logic device (PLD);

determining a plurality of priority groups, wherein the connections are associated with one or more of the priority groups based on the timing slacks; and

routing the connections, for PLD configuration, associated with each priority group, from a highest priority group to a lowest priority group, wherein each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed, wherein the iterative routing for at least one of the plurality of priority groups comprises signal-based routing negotiation comprises reusing a portion of a maze expansion wave for the connections that are associated with the at least one priority group and that are associated with a single signal.

9. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:

determining timing slacks for connections described in a netlist for a programmable logic device (PLD),

determining a plurality of priority groups, wherein the connections are associated with one or more of the priority groups based on the timing slacks, and

routing the connections associated with each priority group, from a highest priority group to a lowest priority group, wherein each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed, wherein the iterative routing for each priority group comprises: updating the timing slacks corresponding to routed connections; and adjusting at least one of the plurality of priority groups based on the updated timing slacks.

10. The system of claim 9 , wherein the iterative routing for at least one of the plurality of priority groups comprises connection-based routing negotiation.

11. The system of claim 9 , wherein the plurality of priority groups are determined by percentages applied to a range of the timing slacks.

12. The system of claim 9 , wherein the plurality of priority groups are determined by percentages applied to a total number of the connections.

13. The system of claim 9 , wherein the lowest priority group includes all the connections.

14. The system of claim 9 , wherein the determining timing slacks comprises determining positions of source and load nodes for the connections and/or estimating signal propagation times between source and load nodes for the connections.

15. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:

determining timing slacks for connections described in a netlist for a programmable logic device (PLD),

determining a plurality of priority groups, wherein the connections are associated with one or more of the priority groups based on the timing slacks, and

routing the connections associated with each priority group, from a highest priority group to a lowest priority group, wherein each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed, wherein the iterative routing for at least one of the plurality of priority groups comprises signal-based routing negotiation comprising reusing a portion of a maze expansion wave for the connections that are associated with the at least one priority group and that are associated with a single signal.

16. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:

determining timing slacks for connections described in a netlist for a programmable logic device (PLD);

determining a plurality of priority groups, wherein the connections are associated with one or more of the priority groups based on the timing slacks; and

routing the connections associated with each priority group, from a highest priority group to a lowest priority group, wherein each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed, wherein the iterative routing for each priority group comprises: updating the timing slacks corresponding to routed connections; and adjusting at least one of the plurality of priority groups based on the updated timing slacks.

Assignments (4)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
SECURITY INTEREST Recorded Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC.; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035309/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2013
From: ZHANG, QINHAI
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 031834/0512 →