Semiconductor defect characterization
View Patent ↗The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects.
1. A method of semiconductor manufacture, comprising:
in a computer for analyzing a wafer having a number of die (N), counting a number (H) of the die that are included in both a subset of the N die, with a number (D) members, having a defect, as identified from an inspection layer analysis of the wafer, and which also are included in a subset of the N die, which are failing, having a number of failing die (F) identified from a fault test of the wafer;
in the computer, dividing H into a number (Hk) of die that are postulated to have a defect that caused a die failure and into a number (Hb) of the die that are postulated to have a defect that did not cause a die failure, wherein the division is based upon the numbers H, D, F, and N, and H=Hk+Hb;
in the computer, calculating a number (Hr) of die that has the same proportionality to F as does D to N;
in the computer, computing a probability (P(H)) of H occurring and a probability (P(Hr)) of Hr occurring; and
adjusting a wafer manufacturing step based at least on P(H) and P(Hr).
2. The method of claim 1 , further comprising:
in the computer, computing a confidence factor based upon a ratio of P(H) and P(Hr).
3. The method of claim 2 , wherein computing the confidence factor is further based upon a logarithm of the ratio.
4. The method of claim 2 , further comprising: in the computer, calculating a confidence-factor-adjusted yield based upon the confidence factor and Hk.
5. The method of claim 4 , wherein the calculation of the confidence-factor-adjusted yield is further based upon N.
6. The method of claim 2 , further comprising repeating the counting, dividing, and computing steps for additional inspection layers for the wafer.
7. The method of claim 6 , further comprising identifying the inspection layers that have confidence factors greater than a threshold.
8. The method of claim 7 , wherein the threshold is at one or greater.
9. The method of claim 7 , further comprising analyzing a wafer map for each of the identified inspection layers, wherein each wafer map classifies the die according to the corresponding inspection layer analysis and fault testing.
10. The method of claim 9 , further comprising adjusting the wafer manufacturing process step based upon the confidence-factor-adjusted yield.
11. The method of claim 1 , wherein computing the probability P(H) comprises using a hypergeometric function.
12. The method of claim 9 , wherein the hypergeometric function equals (F!/(H!*(F−H)!))*((N−F)!/((D−H)!*(N−F−D+H)!))/(N!/(D!*(N−D)!)).
13. The method of claim 1 , wherein computing the probability P(Hr) comprises using a hypergeometric function.
14. A system, comprising:
a computer configured to:
count a number (H) of the die on a wafer that are included in both a number D of die on the wafer that have a defect as identified from an inspection layer analysis and included in a number (F) of failing die on the wafer identified from a fault test;
divide the number H into a number (Hk) of die that are postulated to have a defect that caused a die failure and into a number (Hb) of the die that are postulated to have a defect that did not cause a die failure, wherein the division is based upon the numbers H, D, F, and N;
calculate a number (Hr) of die that has the same proportionality to F as the proportionality of D to N; and
compute a probability (P(H)) of H occurring and a probability (P(Hr)) of Hr occurring.
15. The system of claim 14 , wherein the computer is further configured to compute a confidence factor based upon a ratio between P(H) and P(Hr).
16. The system of claim 15 , wherein the computer is further configured to compute the confidence factor based upon a logarithm of the ratio.
17. The system of claim 14 , wherein the computer is further configured to repeat the counting, dividing, and computing steps for additional inspection layers for the wafer.
18. The method of claim 1 , further comprising:
subsequent to a manufacturing step for a wafer having a number N of die;
performing an inspection analysis to identify the number D of die on the wafer with a defect; and
subsequent to a completion of the manufacturing of the die on the wafer, testing an operability of the die to identify the number F of the die that failed the testing.