Reconfiguration of programmable logic devices
View Patent ↗Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks and corresponding input/output pins, and configuration memory. The PLD also includes registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the PLD.
1. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks and corresponding input/output pins;
configuration memory adapted to store configuration data for configuration of the logic blocks and the input/output blocks;
means for capturing output signal values of the input/output pins before a reconfiguration of the programmable logic device; and
means for providing the captured values on the input/output pins during the reconfiguration of the programmable logic device.
2. The programmable logic device of claim 1 , wherein the means for capturing output signal values of the input/output pins comprise for at least one pin a signal path from the input/output pin to a boundary scan register adapted to store the output signal value on the pin.
3. The programmable logic device of claim 1 , wherein the means for providing the captured values on the input/output pins comprise for at least one pin a boundary scan register adapted to store a captured value for the input/output pin and a signal path from the register to the pin.
4. The programmable logic device of claim 1 , wherein the means for capturing output signal values of the input/output pins comprise for at least one pin a latch coupled to an output bus and adapted to capture the output signal value on the bus in response to a capture signal.
5. The programmable logic device of claim 1 , wherein the means for providing the captured values on the input/output pins comprise for at least one pin a latch adapted to store a captured value for the input/output pin and a signal path from the latch to the pin.
6. The programmable logic device of claim 1 , further comprising:
means for providing user-defined values on the input/output pins during the reconfiguration of the programmable logic device; and
means for selecting for at least one input/output pin between the means for providing user-defined values and the means for capturing output signal values.
7. The programmable logic device of claim 6 , wherein the means for providing user-defined values comprises an internal register.
8. The programmable logic device of claim 1 further comprising:
a user register within a logic block, the user register adapted to store a desired signal value for an input/output pin; and
means for selecting as a signal value for the input/output pin between the user register and the means for capturing output signal values.
9. The programmable logic device of claim 8 , wherein the means for selecting comprises a multiplexer.
10. A method of reconfiguring a programmable logic device, the method comprising:
triggering a reconfiguration of the programmable logic device while configuration memory of the programmable logic device is configured with first configuration data;
capturing output signal values of input/output pins of the programmable logic device before the output signal values change in response to the reconfiguration;
reconfiguring the configuration memory with second configuration data; and
providing the captured output signal values on the input/output pins during the reconfiguration.
11. The method of claim 10 , further comprising providing user-defined values on the input/output pins during the reconfiguration.
12. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks and corresponding input/output pins;
configuration memory adapted to store configuration data for configuration of the logic blocks and the input/output blocks; and
registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the programmable logic device.
13. The programmable logic device of claim 12 , further comprising:
a user register associated with at least one capture register, the user register adapted to store a desired signal value for an input/output pin; and
a multiplexer adapted to select as a signal value for the input/output pin between the user register and the capture register.