Patent Assignment
Reel/Frame 035308/0345
Security Interest
Recorded: 2015-03-24
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(103)
Hysteresis-Based Processing for Applications Such as Signal Bias Monitors
Patent:
7,616,029 →
Application:
11/869,019 →
Dynamic Delay or Advance Adjustment of Oscillating Signal Phase
Patent:
7,586,344 →
Application:
11/872,950 →
Scan Chain Systems and Methods for Programmable Logic Devices
Patent:
7,757,198 →
Application:
11/875,748 →
Single-Ended Output Driver Buffer
Patent:
7,411,414 →
Application:
11/877,434 →
Channel-To-Channel Deskew Systems and Methods
Patent:
8,132,040 →
Application:
11/924,088 →
Programmable Logic Device with Enhanced Logic Block Architecture
Patent:
7,573,291 →
Application:
11/934,711 →
Simultaneous Switching Output Noise Estimation and Reduction Systems and Methods
Patent:
7,895,555 →
Application:
11/937,300 →
Input/Output Placement Systems and Methods to Reduce Simultaneous Switching Output Noise
Patent:
7,788,620 →
Application:
11/937,328 →
Flexible Delay Cell Architecture
Patent:
7,863,931 →
Application:
11/939,787 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,535,253 →
Application:
11/941,006 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
7,902,865 →
Application:
11/941,031 →
Composite Wire Indexing for Programmable Logic Devices
Patent:
7,788,623 →
Application:
11/947,662 →
Integrated Circuit Having Independent Voltage and Process/Temperature Control
Patent:
7,586,325 →
Application:
11/949,130 →
Programmable Level Shifter
Patent:
7,605,609 →
Application:
11/957,598 →
Programmable Logic Device with Built in Self Test
Patent:
7,630,259 →
Application:
11/959,329 →
Process Charging Monitor for Nonvolatile Memory
Patent:
7,646,643 →
Application:
11/970,212 →
Serial Interface for Programmable Logic Devices
Patent:
7,728,625 →
Application:
12/001,600 →
Programmable Logic Device with a Multi-Data Rate Sdram Interface
Patent:
7,787,326 →
Application:
12/019,526 →
Internally Triggered Reconfiguration of Programmable Logic Devices
Patent:
8,069,329 →
Application:
12/021,202 →
Reconfiguration of Programmable Logic Devices
Patent:
7,652,500 →
Application:
12/044,842 →
Wire Mapping for Programmable Logic Devices
Patent:
7,890,913 →
Application:
12/055,170 →
Programmable Logic Devices with Distributed Memory
Patent:
7,459,935 →
Application:
12/060,776 →
Detection of Timing Errors in Programmable Logic Devices
Patent:
7,831,856 →
Application:
12/061,885 →
On-Chip Temperature Sensor for an Integrated Circuit
Patent:
7,661,878 →
Application:
12/099,933 →
Programmable Logic Device with Power-Saving Architecture
Patent:
7,558,143 →
Application:
12/100,859 →
Synchronization of Data Signals and Clock Signals for Programmable Logic Devices
Patent:
7,557,606 →
Application:
12/105,146 →
Programmable Logic Device with Multiple Slice Types
Patent:
7,696,784 →
Application:
12/105,959 →
Power Management Systems and Methods for Programmable Logic Devices
Patent:
7,560,953 →
Application:
12/107,883 →
Formation of High Voltage Transistor with High Breakdown Voltage
Patent:
7,897,448 →
Application:
12/122,489 →
Digital Signal Processing Block Architecture for Programmable Logic Device
Patent:
8,463,832 →
Application:
12/146,042 →
Logic Block Control Architectures for Programmable Logic Devices
Patent:
7,592,834 →
Application:
12/164,265 →
Synchronization of Serial Data Signals
Patent:
8,261,160 →
Application:
12/182,940 →
Selective Loading of Configuration Data into Configuration Memory Cells
Patent:
7,579,865 →
Application:
12/186,027 →
Low-Power Output Driver Buffer Circuit
Patent:
7,605,602 →
Application:
12/188,120 →
Programmable Signal Routing Systems Having Low Static Leakage
Clock Systems and Methods
Patent:
7,663,419 →
Application:
12/273,868 →
Congestion-Driven Placement Systems and Methods for Programmable Logic Devices
Patent:
8,112,731 →
Application:
12/277,217 →
Congestion Estimation for Programmable Logic Devices
Patent:
7,992,120 →
Application:
12/323,974 →
Programmable Logic Device and Method of Testing
Patent:
7,656,193 →
Application:
12/327,128 →
Congestion Estimation Based on Routing Resources of Programmable Logic Devices
Patent:
8,856,718 →
Application:
12/337,502 →
Multi-Priority Placement for Configuring Programmable Logic Devices
Patent:
8,181,139 →
Application:
12/341,929 →
Temperature-Independent, Linear on-Chip Termination Resistance
Patent:
7,714,608 →
Application:
12/370,039 →
Flexible Memory Architectures for Programmable Logic Devices
Patent:
7,957,208 →
Application:
12/389,149 →
Receiver for Differential and Reference Voltage Signaling with Programmable Common Mode
Patent:
7,844,243 →
Application:
12/402,751 →
Routing Signals to Pins of Components in Programmable Logic Devices
Patent:
8,069,431 →
Application:
12/406,772 →
Clock Boosting Systems and Methods
Patent:
8,086,986 →
Application:
12/408,047 →
Dual-Slice Architectures for Programmable Logic Devices
Patent:
7,675,321 →
Application:
12/409,757 →
Efficient Bitstream Compression
Patent:
7,808,405 →
Application:
12/413,787 →
Soft Error Upset Hardened Integrated Circuit Systems and Methods
Patent:
7,741,865 →
Application:
12/430,848 →
Register Data Retention Systems and Methods During Reprogramming of Programmable Logic Devices
Patent:
7,876,125 →
Application:
12/464,822 →
Reading an External Memory Device to Determine Its Interface Characteristics for Configuring a Programmable Logic Device
Patent:
7,868,654 →
Application:
12/465,444 →
Transparent Field Reconfiguration for Programmable Logic Devices
Patent:
7,737,723 →
Application:
12/467,800 →
Fpga Having Low Power, Fast Carry Chain
Programmable Logic Devices with Custom Identification Systems and Methods
Patent:
7,702,977 →
Application:
12/480,565 →
In-System Reconfigurable Circuit for Mapping Data Words of Different Lengths
Patent:
8,165,164 →
Application:
12/494,822 →
Power Management for Integrated Circuits Such as Programmable Logic Devices
Patent:
7,724,029 →
Application:
12/502,141 →
Programmable Logic Device Providing Serial Peripheral Interfaces
Patent:
7,768,300 →
Application:
12/511,388 →
Clock Delay and Skew Control Systems and Methods
Patent:
8,255,733 →
Application:
12/512,944 →
Oscillator Tuning for Phase-Locked Loop Circuit
Patent:
7,969,248 →
Application:
12/512,961 →
Distributed Front-End Fifo for Source-Synchronous Interfaces with Non-Continuous Clocks
Patent:
7,808,855 →
Application:
12/538,810 →
Auto Recovery from Volatile Soft Error Upsets (Seus)
Patent:
8,010,871 →
Application:
12/561,140 →
Redundant Configuration Memory Systems and Methods
Patent:
7,746,107 →
Application:
12/564,781 →
Clock Distribution Chip
Patent:
8,122,277 →
Application:
12/578,470 →
Clock Distribution Chip
Patent:
8,112,656 →
Application:
12/578,492 →
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
Patent:
7,985,656 →
Application:
12/607,333 →
Shallow Trench Isolation (Sti) with Trench Liner of Increased Thickness
Patent:
7,989,911 →
Application:
12/607,868 →
Flash Memory Array with Independently Erasable Sectors
Patent:
8,059,470 →
Application:
12/611,262 →
Programmable Logic Device with Built in Self Test
Patent:
7,944,765 →
Application:
12/626,289 →
Programmable Logic Device and Methods for Providing Multi-Boot Configuration Data Support
Patent:
8,060,784 →
Application:
12/630,163 →
Combined Variable Gain Amplifier and Analog Equalizer Circuit
Patent:
8,200,179 →
Application:
12/637,884 →
Separate Configuration of I/O Cells and Logic Core in a Programmable Logic Device
Patent:
8,040,152 →
Application:
12/698,283 →
Latency Measurements for Wireless Communications
Patent:
7,924,054 →
Application:
12/706,227 →
Method and Devices for Storing a Security Key Using Programmable Fuses
Patent:
7,834,652 →
Application:
12/709,685 →
Comparator with Jitter Mitigation
Patent:
8,040,159 →
Application:
12/729,952 →
Configuring Multiple Programmable Logic Devices with Serial Peripheral Interfaces
Patent:
8,384,427 →
Application:
12/752,455 →
Bondwire Configuration for Reduced Crosstalk
Patent:
8,664,774 →
Application:
12/757,087 →
Programmable Logic Device Programming Verification Systems and Methods
Patent:
8,108,754 →
Application:
12/786,359 →
Shared-Array Multiple-Output Digital-to-Analog Converter
Patent:
8,164,499 →
Application:
12/813,540 →
Delaying Data Signals
Patent:
8,441,292 →
Application:
12/813,573 →
Soft Error Upset Hardened Integrated Circuit Systems and Methods
Patent:
7,868,646 →
Application:
12/818,544 →
Composite Wire Indexing for Programmable Logic Devices
Patent:
8,286,116 →
Application:
12/871,764 →
Bitline Floating Circuit for Memory Power Reduction
Patent:
8,351,287 →
Application:
12/976,412 →
Triggered Sense Amplifier
Patent:
8,477,549 →
Application:
12/976,520 →
Blocking Memory Readback In A Programmable Logic Device
Patent:
8,522,126 →
Application:
12/977,011 →
Serializer with Odd Gearing Ratio
Patent:
8,274,412 →
Application:
12/987,393 →
Pre-Configuration Programmability of I/O Circuitry
Patent:
8,384,428 →
Application:
13/006,622 →
Programmable Buffer
Patent:
8,324,934 →
Application:
13/007,688 →
Low-Power, Glitch-Less, Configurable Delay Element
Patent:
8,248,136 →
Application:
13/007,804 →
Wire Mapping for Programmable Logic Devices
Patent:
8,104,009 →
Application:
13/026,555 →
Compression and Decompression of Configuration Data Using Repeated Data Frames
Patent:
8,058,898 →
Application:
13/034,174 →
Low-Voltage Current Sense Amplifier
Patent:
8,654,600 →
Application:
13/037,703 →
Programmable Logic Device Wakeup Using a General Purpose Input/Output Port
Patent:
8,368,424 →
Application:
13/038,259 →
Variable Response Mode for Synchronous Data Read
Patent:
8,816,718 →
Application:
13/038,270 →
Voltage Discharge Circuit Having Divided Discharge Current
Patent:
8,553,463 →
Application:
13/052,142 →
Safe Programming of Key Information into Non-Volatile Memory for a Programmable Logic Device
Patent:
8,319,521 →
Application:
13/076,300 →
Power Control Block with Output Glitch Protection
Patent:
8,314,634 →
Application:
13/079,578 →
Phase Locked Loop Circuit with Selectable Feedback Paths
Patent:
8,531,222 →
Application:
13/079,595 →
Latency Measurements for Wireless Communications
Patent:
8,138,790 →
Application:
13/083,889 →
Flexible Updating of Multi-Bit Registers
Patent:
8,441,284 →
Application:
13/154,885 →
Voltage Regulators with a Shared Capacitor
Patent:
8,547,075 →
Application:
13/155,547 →
Integrated Circuit Design Software with Cross Probing Between Tool Graphical User Interfaces (Guis)
Patent:
8,555,217 →
Application:
13/164,108 →
Alignment Circuit for Parallel Data Streams
Patent:
8,495,264 →
Application:
13/178,536 →
Simultaneous Development of Complementary Ic Families
Patent:
8,539,409 →
Application:
13/178,599 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →