Flexible memory architectures for programmable logic devices
In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.
1. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks;
volatile memory adapted to store configuration data for configuration of the logic blocks and input/output blocks and further adapted to store user data;
non-volatile memory;
first and second data ports adapted to provide external device access to the non-volatile memory; and
an arbitration bus coupled between the first and second data ports and the non-volatile memory, the bus adapted to arbitrate between the two data ports in accessing the non-volatile memory;
wherein the non-volatile memory is adapted to store user data from at least one of the data ports and is further adapted to store user data from the volatile memory.
2. The programmable logic device of claim 1 , wherein the non-volatile memory is further adapted to transfer the user data stored therein to at least one of the data ports.
3. The programmable logic device of claim 1 , wherein the non-volatile memory is further adapted to transfer user data stored therein to the volatile memory.
4. The programmable logic device of claim 1 , wherein the volatile memory includes configuration memory for storing configuration data and embedded block RAM for storing user data.
5. The programmable logic device of claim 1 , wherein the non-volatile memory includes tag memory.
6. The programmable logic device of claim 1 , wherein the first data port includes a serial peripheral interface.
7. The programmable logic device of claim 1 , wherein the first data port includes a serial peripheral interface and the second data port includes a JTAG interface.
8. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks;
volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks;
embedded block RAM adapted to store user data;
flash memory having at least a first partition and a second partition;
a first data port adapted to provide external device access to the first partition of the non-volatile memory;
a second data port adapted to provide external access to the first partition of the flash memory; and
an arbitration bus coupled between the first and second data ports and the first partition of the flash memory, the bus adapted to arbitrate between the two data ports in accessing the flash memory,
wherein the flash memory is adapted to store within the first partition user data from at least one of the data ports and is further adapted to store within the second partition user data from the embedded block RAM.
9. The programmable logic device of claim 8 , wherein the first data port includes a serial peripheral interface and the second data port includes a JTAG interface.
10. The programmable logic device of claim 8 , wherein the flash memory includes a third partition adapted to store configuration data for transfer to the volatile memory.
11. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input/output blocks;
volatile memory adapted to store configuration data for configuration of the logic blocks and input/output blocks and further adapted to store user data;
non-volatile memory having at least a first part and a second part;
first and second data ports each adapted to provide external device access to the first part of the non-volatile memory; and
an arbitration bus coupled between the first and second data ports and the first part of the non-volatile memory, the bus adapted to arbitrate between the two data ports in accessing the non-volatile memory,
wherein the non-volatile memory is adapted to store within the first part user data from at least one of the data ports and is further adapted to store within the second part user data from the volatile memory.
12. The programmable logic device of claim 11 , wherein the first and second parts of the non-volatile memory are first and second partitions of the non-volatile memory.
13. The programmable logic device of claim 11 , wherein the first and second parts of the non-volatile memory are first and second non-volatile memories.
14. The programmable logic device of claim 11 , wherein the non-volatile memory includes a third part adapted to store configuration data for transfer to the volatile memory.
15. The programmable logic device of claim 11 , wherein the non-volatile memory is further adapted to transfer user data stored in the first part to at least one of the data ports.
16. The programmable logic device of claim 11 , wherein the non-volatile memory is further adapted to transfer user data stored in the second part to the volatile memory.
17. The programmable logic device of claim 11 , wherein the first data port includes a serial peripheral interface and the second data port includes a JTAG interface.
18. The programmable logic device of claim 11 , wherein the volatile memory includes configuration memory for storing configuration data and embedded block RAM for storing user data.