Flash memory array with independently erasable sectors
View Patent ↗In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set of shared bitlines, a first row driver circuit is coupled to the set of word lines of the first subarray, and a second row driver circuit is coupled to the set of word lines of the second subarray. The first and second row driver circuits are operable to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray. The two row driver circuits are further operable to enable the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.
1. An integrated circuit comprising:
a flash memory array including at least first and second subarrays of memory cells, the subarrays including a set of shared bitlines and separate sets of word lines;
a bitline driver circuit coupled to the set of shared bitlines of the first and second subarrays;
a first row driver circuit coupled to the set of word lines of the first subarray; and
a second row driver circuit coupled to the set of word lines of the second subarray,
wherein the first and second row driver circuits are operable to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray and the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.
2. The integrated circuit of claim 1 , wherein the first row driver circuit is operable to drive the set of word lines of the first subarray to a desired voltage while the second row driver circuit is operable to tri-state the set of word lines of the second subarray, and the first row driver circuit is operable to tri-state the set of word lines of the first subarray while the second row driver circuit is operable to drive the set of word lines of the second subarray to a desired voltage.
3. The integrated circuit of claim 1 , wherein the bitline driver circuit is operable with the first and second row driver circuits to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray and the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.
4. The integrated circuit of claim 1 including a plurality of erase voltage taps connected with the first and second subarrays.
5. The integrated circuit of claim 1 , wherein the memory cells of the first and second subarrays are implemented together in a common P-well encapsulated by an N-well.
6. The integrated circuit of claim 1 , wherein the memory cells of the first and second subarrays are implemented in separate P-wells encapsulated by an N-well.
7. The integrated circuit of claim 1 , wherein the first row driver circuit comprises:
a plurality of high voltage level translators adapted to provide a plurality of high voltage logic signals in response to a plurality of low voltage logic signals; and
a plurality of high voltage transistors adapted to selectively tri-state one of the word lines or drive the word line with the first voltage in response to the high voltage logic signals.
8. The integrated circuit of claim 1 including:
a third subarray of memory cells including the set of shared bitlines and a separate set of wordlines; and
a third row driver circuit, coupled to the set of wordlines of the third subarray,
wherein the third row driver circuit is operable to enable the memory cells of the third subarray to be erased independently of the memory cells of the first and second subarrays.
9. The integrated circuit of claim 1 , wherein the integrated circuit is a programmable logic device (PLD).
10. An integrated circuit comprising:
a flash memory array including at least first and second subarrays of memory cells, the subarrays having shared bitlines and separate word lines;
a bitline driver circuit coupled to the shared bitlines of the first and second subarrays; and
means coupled to the word lines of the first and second subarrays for enabling the memory cells of the first subarray to be erased independently of the memory cells of the second subarray and the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.
11. A method of erasing memory cells of a flash memory array, the method comprising:
providing at least first and second subarrays of memory cells in the flash memory array,
the subarrays having a set of shared bitlines and separate sets of word lines;
driving the set of word lines of the first subarray to a first desired voltage;
driving the set of word lines of the second subarray to a high-impedance state; and
providing a second desired voltage to erase voltage taps connected with the first and second arrays,
wherein in response to the first and second voltages and the high-impedance state, the memory cells of the first subarray are erased but not the memory cells of the second subarray.
12. The method of claim 11 , wherein the first voltage is a negative voltage and the second voltage is a positive voltage.
13. The method of claim 12 , wherein the first voltage is in a range of approximately −5V to −10V and the second voltage is in a range of approximately 9V to 10V.