Latency measurements for wireless communications
View Patent ↗A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.
1. A programmable logic device (PLD), comprising:
a plurality of SERDES channels;
a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and
a timing measurement circuit configured to measure a time elapsed between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.
2. The PLD of claim 1 , wherein the PLD comprises a field programmable gate array (FPGA).
3. The PLD of claim 1 , wherein the interface is a Common Public Radio Interface (CPRI).
4. The PLD of claim 1 , wherein the interface is a Open Base Station Architecture Initiative (OBSAI) interface.
5. The PLD of claim 1 , wherein the timing measurement circuit comprises hardwired logic resources.
6. The PLD of claim 5 , wherein the hardwired logic resources are within the SERDES channels such that each SERDES channels includes a timing measurement circuit.
7. The PLD of claim 1 , wherein the timing measurement circuit includes a first multiplexer that selects for the detection of the first timing point from a first plurality of locations in the PLD.
8. The PLD of claim 7 , wherein the timing measurement circuit includes a second multiplexer that selects for the detection of the second timing point from a second plurality of locations in the PLD.
9. THE FPGA of claim 2 , wherein the SERDES channels include First-In-First-Out (FIFO) buffers, and wherein the data words flow through the FIFO buffers.
10. A field programmable gate array (FPGA), comprising:
a SERDES channel including a timing measurement circuit; and
a programmable fabric configured to implement a Common Public Radio Interface (CPRI) interface, wherein the timing measurement circuit is configured to determine a time elapsed between a detection of an incoming frame to the CPRI interface from an external component and a detection of a corresponding outgoing frame to the external component from the programmable fabric.
11. The FPGA of claim 10 wherein the timing measurement circuit includes a counter clocked by a clock of at least 600 MHz or higher in frequency.
12. The FPGA of claim 11 , wherein the counter begins counting responsive to the clock upon detection of the incoming frame.
13. The FPGA of claim 11 , wherein the counter finishes counting responsive to the clock upon detection of the corresponding outgoing frame.
14. The FPGA of claim 11 , wherein the timing measurement circuit further includes a status register to hold a count determined by the counter, and wherein the count represents the time elapsed.
15. The FPGA of claim 14 , wherein the programmable fabric controls a reset of the status register.
16. A programmable logic device, comprising:
a programmable fabric;
hard logic within the programmable logic device coupled to the programmable fabric; and
a timing measurement circuit within the programmable logic device adapted to measure a latency of a data path configured between two points in the programmable fabric and/or hard logic.
17. The programmable logic device of claim 16 , wherein the timing measurement circuit includes a counter clocked by a clock of at least 600 MHz or higher in frequency.
18. The programmable logic device of claim 17 , wherein the timing measurement circuit further includes a status register to hold a count determined by the counter, and wherein the count represents the latency.
19. The programmable logic device of claim 18 , wherein the programmable fabric is configured to control a reset of the status register.
20. The programmable logic device of claim 16 , wherein the timing measurement circuit is implemented in the hard logic.