Soft error upset hardened integrated circuit systems and methods
View Patent ↗In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.
1. A programmable logic device (PLD) comprising:
a plurality of configuration memory cells adapted to store configuration data bits of a user design, each cell having at least one input node to receive a configuration bit and Q and QN output nodes to provide the configuration bit;
a plurality of address lines coupled to the configuration memory cells;
a plurality of bitlines coupled to the input nodes of the configuration memory cells;
logic circuitry coupled to the address lines and the bitlines of the memory cell array and adapted to select between a soft error upset (SEU)-hardened mode and a programmable mode for the memory cells, the logic circuitry adapted to force the address lines and bitlines to predetermined logical values in the SEU-hardened mode, wherein the address lines and bitlines force the Q and QN output nodes of each memory cell to predetermined logical values; and
a mask programmable connection associated with each memory cell for connecting one of the Q and ON output nodes of the cell to configurable resources of the PLD,
wherein in the SEU-hardened mode and with the mask programmable connections programmed, the memory cells provide configuration data bits having the predetermined logical values of the connected Q and QN output nodes to the configurable resources.
2. The programmable logic device of claim 1 , wherein the array plurality of memory cells comprises a row of memory cells.
3. The programmable logic device of claim 1 , wherein the memory cells are six-transistor SRAM cells.
4. The programmable logic device of claim 1 , wherein the logic circuitry is adapted to force the address lines to a same logical value in the SEU-hardened mode.
5. The programmable logic device of claim 1 , wherein the logic circuitry is adapted to force the bitlines to a same logical value in the SEU-hardened mode.
6. The programmable logic device of claim 1 , wherein the logic circuitry is adapted to allow each memory cell to be programmed in a conventional manner in the programming mode.
7. The programmable logic device of claim 1 , wherein the mask programmable connections comprise metal layers within the PLD.
8. The programmable logic device of claim 1 including:
an address shift register coupled to the address lines;
a data shift register coupled to the bitlines; and
the logic circuitry includes a first logic gate associated with each address line and a second logic gate associated with each bitline,
wherein the logic gates are responsive to a control signal such that in the SEU-hardened mode the logic gates force the address lines and bitlines to predetermined logical values, wherein the address lines and bitlines force the Q and QN output nodes of each memory cell to predetermined logical values, and in the programming mode the logic gates allow each memory cell to be programmed in a conventional manner through the address shift register and data shift register.
9. The programmable logic device of claim 8 , wherein the first logic gates are included within an address shift register coupled to the address lines.
10. The programmable logic device of claim 8 , wherein the second logic gates are included within a data shift register coupled to the bitlines.
11. The programmable logic device of claim 1 , wherein the logic circuitry includes a logic gate associated with each address line and responsive to a control signal such that in the SEU-hardened mode the address line is driven by the logic gate to a predetermined logical value and in the programming mode the address line is not driven by the logic gate to the predetermined logical value.
12. The programmable logic device of claim 1 , wherein the logic circuitry includes a logic gate associated with each bitline and responsive to a control signal such that in the SEU-hardened mode the bitline is driven by the logic gate to a predetermined logical value and in the programming mode the bitline is not driven by the logic gate to the predetermined logical value.
13. The programmable logic device of claim 1 , wherein each memory cell of the array has output paths from the Q and QN output nodes of the cell, and the output path of a first cell is routed to an output node of a second cell and the output path of the second cell is routed to an output node of the first cell.
14. A method of hardening configuration memory cells of a programmable logic device (PLD) against soft error upsets (SEUs), the method comprising:
providing an array of configuration memory cells adapted to store configuration data bits, each cell having at least one input node to receive a configuration bit and Q and QN output nodes to provide the configuration data bit;
obtaining a user design for the PLD; and
mask programming connections between the Q and QN output nodes of the memory cells and configurable resources of the PLD such that the cells provide the configuration data bits of the user design to the configurable resources when the Q and QN output nodes of the memory cells are programmed to and maintained at predetermined logical values.
15. The method of claim 14 , wherein the predetermined logical values are the same logical values for each Q output node and the same logical values for each QN output node.
16. A programmable logic device (PLD) comprising:
a plurality of configuration memory cells adapted to store configuration data bits, each cell having at least one input node to receive a configuration data bit and Q and QN output nodes to provide the configuration data bit;
a plurality of address lines coupled to the configuration memory cells;
a plurality of bitlines coupled to the input nodes of the configuration memory cells;
logic circuitry adapted to force the address lines and bitlines to predetermined logical values in response to a control signal, wherein the address lines and bitlines force the Q and QN output nodes of each memory cell to predetermined logical values; and
a mask programmable connection between each memory cell and configurable resources of the PLD for connecting one of the Q and QN output nodes of the memory cell to the configurable resources.
17. The programmable logic device of claim 16 , wherein the mask programmable connections of each memory cell are programmed to connect one of the Q and QN output nodes of the memory cell to the configurable resources.
18. The programmable logic device of claim 17 , wherein the memory cells are adapted to provide configuration data bits having the predetermined logical values of the connected Q and QN nodes to the configurable resources when the logic circuitry forces the address lines and bitlines to their predetermined logical values.
19. The programmable logic device of claim 16 , wherein the logic circuitry is adapted to force the address lines to a same logical value.
20. The programmable logic device of claim 16 , wherein the logic circuitry is adapted to force the bitlines to a same logical value.
21. The programmable logic device of claim 16 , wherein the logic circuitry, through the address lines and bitlines, is adapted to force the Q output nodes of each memory cell to a same logical value and the QN output nodes of each memory cell to a same logical value.
22. The programmable logic device of claim 16 , wherein the logic circuitry includes logic gates coupled between the address lines and the configuration memory cells and the bitlines and the configuration memory cells, the logic gates responsive to the control signal to force the address lines and bitlines to the predetermined logical values.