IP Library Granted Patent US 8,286,116
Granted Patent B1
US 8,286,116 · App. 12/871,764 · Granted Oct 9, 2012

Composite wire indexing for programmable logic devices

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Quick Facts
Patent No.
US 8,286,116
App. No.
12/871,764
Granted
Oct 9, 2012
Kind
B1
Abstract

Various techniques are disclosed to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes associating segmented wires of the PLD with a plurality of wire index values based on connections identified by interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Claims (46)

1. A computer-implemented method of referencing wires of a programmable logic device (PLD), the method comprising:

identifying in a computer a plurality of tiles within the PLD, wherein a tile corresponds to a tile template, the tile template including one or more programmable logic blocks, switches, and segmented wires;

selecting in the computer first and second adjacent tiles from the identified tiles;

selecting in the computer first and second tile templates corresponding to the first and second tiles;

comparing in the computer a segmented wire of the first tile template to a segmented wire of the second tile template to determine whether the segmented wires are connected; and

for a wire connection found between the first and second tile templates, creating in the computer an interface template and including in the interface template a reference to the wire connection.

2. The method of claim 1 , wherein the reference to the wire connection includes an ordered pair of the connected segmented wires.

3. The method of claim 1 including:

associating in the computer the connected segmented wires of the reference with a same wire index value.

4. The method of claim 3 including for each additional reference to a wire connection in the interface template:

incrementing the wire index value; and

associating in the computer the connected segmented wires of the reference with the incremented wire index value.

5. The method of claim 3 including:

setting in the computer a wire index value to a current value;

identifying in the computer the connected segmented wires having the current wire index value; and

creating in the computer a composite wire from the identified segmented wires.

6. The method of claim 5 including:

incrementing the current wire index value; and

repeating the identifying, creating and incrementing steps to create additional composite wires.

7. The method of claim 5 , wherein the setting step includes setting the wire index value to an initial value.

8. The method of claim 5 , wherein the composite wire is adapted to interconnect programmable logic blocks of the PLD.

9. The method of claim 5 including:

generating in the computer configuration data for the PLD, wherein the configuration data includes a reference to the composite wire.

10. A non-transient computer readable medium on which is stored a computer program that when executed by a computer performs a method of referencing wires of a programmable logic device (PLD), the method comprising:

identifying in a computer a plurality of tiles within the PLD, wherein a tile corresponds to a tile template, the tile template including one or more programmable logic blocks, switches, and segmented wires;

selecting in the computer first and second adjacent tiles from the identified tiles;

selecting in the computer first and second tile templates corresponding to the first and second tiles;

comparing in the computer a segmented wire of the first tile template to a segmented wire of the second tile template to determine whether the segmented wires are connected; and

for a wire connection found between the first and second tile templates, creating in the computer an interface template and including in the interface template a reference to the wire connection.

11. The computer readable medium of claim 10 , wherein the reference to the wire connection includes an ordered pair of the connected segmented wires.

12. The computer readable medium of claim 10 , wherein the method includes:

associating in the computer the connected segmented wires of the reference with a same wire index value.

13. The computer readable medium of claim 10 , wherein the method includes for each additional reference to a wire connection in the interface template:

incrementing the wire index value; and

associating in the computer the connected segmented wires of the reference with the incremented wire index value.

14. The computer readable medium of claim 10 , wherein the method includes:

setting in the computer a wire index value to a current value;

identifying in the computer the connected segmented wires having the current wire index value; and

creating in the computer a composite wire from the identified segmented wires.

15. The computer readable medium of claim 14 , wherein the method includes:

incrementing the current wire index value; and

repeating the identifying, creating and incrementing steps to create additional composite wires.

16. The computer-readable medium of claim 14 , wherein the setting step includes setting the wire index value to an initial value.

17. The computer readable medium of claim 14 , wherein the composite wire is adapted to interconnect programmable logic blocks of the PLD.

18. The computer readable medium of claim 14 , wherein the method includes:

generating in the computer configuration data for the PLD, wherein the configuration data includes a reference to the composite wire.

Assignments (4)
SECURITY INTEREST Recorded May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
SECURITY INTEREST Recorded Mar 24, 2015
From: LATTICE SEMICONDUCTOR CORPORATION; SIBEAM, INC; SILICON IMAGE, INC.; DVDO, INC.
To: JEFFERIES FINANCE LLC
Reel/Frame 035308/0345 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2010
From: ENDO, TOSHIKAZU; KANG, BYUNG-KYOO; ZHOU, GUANQU
To: LATTICE SEMICONDUCTOR CORPORATION
Reel/Frame 024911/0983 →