Receiver for differential and reference voltage signaling with programmable common mode
View Patent ↗In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.
1. A mux circuit for a receiver, wherein:
the mux circuit is adapted to receive a plurality of input signals (e.g., PAD 1 , Vref 1 , . . . , Vrefn) and to select one of the plurality of input signals for application to the receiver;
the mux circuit comprises:
a transmission gate (e.g., 202 ) connected between a first pad (e.g., PAD 1 ) and an output of the mux circuit (e.g., MUXOUT), wherein the transmission gate comprises a p-type transistor connected (i) at its channel nodes between the first pad and the output of the mux circuit and (ii) to receive a control signal at its gate node; and
control circuitry for the p-type transistor adapted to implement a threshold reduction filter that ensures that a maximum voltage level at the output of the mux circuit is at least a threshold below a power supply voltage for the mux circuit.
2. The mux circuit of claim 1 , wherein the control circuitry is adapted to chop off an input signal applied to the first pad that is above a specific level.
3. The mux circuit of claim 1 , wherein the control circuitry comprises:
a p-type transistor (e.g., 220 ) and an n-type transistor (e.g., 224 ) connected in series between a first reference voltage (e.g., psub) and a reference ground voltage (e.g., gnd), wherein:
a common node (e.g., OFFPAD 1 ) between the p-type and n-type transistors is connected to the gate node of the p-type transistor in the transmission gate;
the gate nodes of the p-type and n-type transistors is connected to receive a configuration-based control signal; and
the first reference voltage is also the substrate voltage for the p-type transistor in the transmission gate.
4. The mux circuit of claim 3 , wherein the configuration-based control signal is generated by a logic gate (e.g., 218 ) adapted to generate the configuration-based control signal based on (i) a first configuration control signal (e.g., ENABLEPAD 1 ) identifying whether or not the input signal applied to the first pad is to be presented at the output of the mux circuit and (ii) a second configuration control signal (e.g., LVPAD 1 ) identifying whether or not the input signal corresponds to a low common-mode voltage.