Programmable logic device with built in self test
View Patent ↗In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A built in self test (BIST) circuit is operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory. The BIST circuit may include a finite state machine for performing at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase. A memory controller responsive to the finite state machine is operable to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.
1. An integrated circuit comprising:
volatile memory;
nonvolatile memory;
a data shift register operable to read data from the nonvolatile memory and to read data from and write data to the volatile memory; and
a built in self test (BIST) circuit operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory.
2. The integrated circuit of claim 1 , wherein the BIST circuit includes:
a finite state machine operable to perform at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase; and
a memory controller responsive to the finite state machine to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.
3. The integrated circuit of claim 2 , wherein the finite state machine is included within configuration logic of the integrated circuit, the finite state machine responsive to test instructions received by the configuration logic.
4. The integrated circuit of claim 1 , wherein the data shift register is operable to read data from the nonvolatile memory and to write the read data to the volatile memory.
5. The integrated circuit of claim 1 , wherein the data shift register is operable to test the volatile memory.
6. The integrated circuit of claim 1 , wherein the BIST circuit is operable to test the nonvolatile memory simultaneously with the data shift register reading data from and writing data to the volatile memory.
7. The integrated circuit of claim 1 , wherein the BIST circuit is operable to test the nonvolatile memory by writing data to and reading data from the nonvolatile memory.
8. The integrated circuit of claim 1 , wherein the nonvolatile memory is a flash memory array and the volatile memory is a static random access memory (SRAM) array.
9. The integrated circuit of claim 1 , wherein the integrated circuit is a programmable logic device.
10. An integrated circuit comprising:
volatile memory;
nonvolatile memory;
a data shift register operable to read data from the nonvolatile memory and to read data from and write data to the volatile memory; and
a built in self test (BIST) circuit operable to test the nonvolatile memory without use of the data shift register.
11. The integrated circuit of claim 10 , wherein the BIST circuit includes a finite state machine operable to perform at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase.
12. A programmable logic device comprising:
volatile configuration memory for configuring the programmable logic device;
nonvolatile memory operable to store configuration data for the configuration memory;
a data shift register operable to read data from the nonvolatile memory and to write the read data to the configuration memory; and
a built in self test (BIST) circuit operable to test the nonvolatile memory by writing data to and reading data from the nonvolatile memory without use of the data shift register.
13. The integrated circuit of claim 12 , wherein the BIST circuit includes a finite state machine operable to perform at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase.