Programmable logic device with a multi-data rate SDRAM interface
View Patent ↗Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
1. Within a programmable logic device (PLD) having an internal clock, a multi-date rate SDRAM interface for multi-date rate SDRAM, the multi-date rate SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface comprising:
a DQS clock tree;
a slave delay circuit adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, the slave delay circuit responsive to a control signal in providing the amount of phase shift; and
a master delay circuit adapted to generate the control signal for the slave delay circuit, the master delay circuit further adapted to compare the internal clock with a delayed version of the internal clock in setting the value of the control signal, the master delay circuit including a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
2. The multi-date rate SDRAM interface of claim 1 , wherein the master delay circuit comprises a delay-locked loop (DLL).
3. The multi-date rate SDRAM interface of claim 1 , wherein the delay line includes at least four instantiations of the slave delay circuit and at least four facsimiles of the DQS clock tree.
4. The multi-date rate SDRAM interface of claim 1 , wherein within the delay line a facsimile of the DQS clock tree follows each instantiation of the slave delay circuit.
5. The multi-date rate SDRAM interface of claim 1 , wherein the interface is a double date rate (DDR) interface.
6. Within a programmable logic device (PLD) having an internal clock, a multi-date rate SDRAM interface for multi-date rate SDRAM, the multi-date rate SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface comprising:
a DQS clock tree;
a slave delay circuit adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree; and
a delay-locked loop (DLL) adapted to control the slave delay circuit, the DLL including a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
7. The multi-date rate SDRAM interface of claim 6 , wherein the delay line includes at least four instantiations of the slave delay circuit and at least four facsimiles of the DQS clock tree.
8. The multi-date rate SDRAM interface of claim 6 , wherein within the delay line a facsimile of the DQS clock tree follows each instantiation of the slave delay circuit.
9. The multi-date rate SDRAM interface of claim 6 , wherein the DLL is further adapted to compare the internal clock with a delayed version of the internal clock in setting the value of a control signal for the slave delay element, the DLL further including a latch for latching the value of the control signal before the signal's application to the slave delay element.
10. The multi-date rate SDRAM interface of claim 6 , wherein the DLL is further adapted to compare the internal clock with a delayed version of the internal clock in setting the value of a control signal for the slave delay element, the DLL further including a variable delay circuit for adjusting the value of the control signal before the signal's application to the slave delay element.
11. The multi-date rate SDRAM interface of claim 6 , wherein the interface is a double date rate (DDR) interface.
12. Within a programmable logic device (PLD) having an internal clock, a multi-date rate SDRAM interface for multi-date rate SDRAM, the multi-date rate SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface comprising:
a DQS clock tree;
a slave delay circuit adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, the slave delay circuit responsive to a control signal in providing the amount of phase shift; and
a delay-locked loop (DLL) adapted to generate the control signal for the slave delay circuit, the DLL further adapted to compare the internal clock with a delayed version of the internal clock in setting the value of the control signal, the DLL including:
a delay line adapted to provide the delayed version of the internal clock, the delay line comprising at least four instantiations of the slave delay circuit, each instantiation followed by a facsimile of the DQS clock tree;
a latch for latching the value of the control signal; and
a variable delay circuit for adjusting the value of the latched control signal before the signal's application to the slave delay element.
13. The multi-date rate SDRAM interface of claim 12 , wherein the interface is a double date rate (DDR) interface.