Logic block control architectures for programmable logic devices

1. A programmable logic device comprising:

configuration memory adapted to store configuration data; and

a plurality of programmable logic blocks, at least one programmable logic block including:

a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register; and

control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data including multiplexer control signals stored within the configuration memory, the control logic including a first set of two or more multiplexers for selecting control signals at the programmable block level, a second set of two or more multiplexers for selecting control signals at the dual-slice block level, and a third set of two or more multiplexers for selecting control signals at the register level.

2. The programmable logic device of claim 1 , wherein the dual-slice logic block further includes:

a first routing circuit coupled to each of the LUTs within the first and second slices and adapted to share outputs of the dual-slice logic block among the LUTs; and

a second routing circuit coupled to each of the LUTs within the first and second slices and adapted to share inputs of the dual-slice logic block among the LUTs.

3. The programmable logic device of claim 1 , wherein each set of multiplexers is adapted to select two or more control signals as a bundle.

4. The programmable logic device of claim 1 , wherein each set of multiplexers is adapted to select two or more control signals independently.

5. The programmable logic device of claim 1 , wherein at least one set of multiplexers is adapted to select control signals as a bundle and at least one set of multiplexers is adapted to select control signals independently.

6. The programmable logic device of claim 1 , wherein each of the sets of multiplexers is adapted to select a clock signal, an enable signal, and a local set/reset signal.

7. A programmable logic device comprising:

configuration memory adapted to store configuration data including multiplexer control signals; and

a plurality of programmable logic blocks, at least one programmable logic block including:

a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register;

a first routing circuit coupled to each of the LUTs within the first and second slices and adapted to share outputs of the dual-slice logic block among the LUTs; and

a second routing circuit coupled to each of the LUTs within the first and second slices and adapted to share inputs of the dual-slice logic block among the LUTs; and

control logic including multiplexers adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to multiplexer control signals stored within the configuration memory, the control logic including a first set of two or more multiplexers for selecting control signals at the programmable block level, a second set of two or more multiplexers for selecting control signals at the dual-slice block level, and a third set of two or more multiplexers for selecting control signals at the register level.

8. The programmable logic device of claim 7 , wherein each set of multiplexers is adapted to select two or more control signals as a bundle.

9. The programmable logic device of claim 7 , wherein each set of multiplexers is adapted to select two or more control signals independently.

10. The programmable logic device of claim 7 , wherein at least one set of multiplexers is adapted to select control signals as a bundle and at least one set of multiplexers is adapted to select control signals independently.

11. The programmable logic device of claim 7 , wherein each of the sets of multiplexers is adapted to select a clock signal, an enable signal, and a local set/reset signal.

12. A programmable logic device comprising:

configuration memory adapted to store configuration data including multiplexer control signals; and

a plurality of programmable logic blocks, at least one programmable logic block including:

a plurality of multi-slice logic blocks, each multi-slice logic block including at least first and second slices, each slice including at least two lookup tables (LUTs) and a register; and

control logic including multiplexers adapted for selecting control signals separately at a programmable block level, a multi-slice block level, and a register level, the control logic responsive to multiplexer control signals stored within the configuration memory, the control logic including a first set of two or more multiplexers for selecting control signals at the programmable block level, a second set of two or more multiplexers for selecting control signals at the multi-slice block level, and a third set of two or more multiplexers for selecting control signals at the register level.

13. The programmable logic device of claim 12 , wherein each set of multiplexers is adapted to select two or more control signals as a bundle.

14. The programmable logic device of claim 12 , wherein each set of multiplexers is adapted to select two or more control signals independently.

15. The programmable logic device of claim 12 , wherein at least one set of multiplexers is adapted to select control signals as a bundle and at least one set of multiplexers is adapted to select control signals independently.

16. The programmable logic device of claim 12 , wherein each of the sets of multiplexers is adapted to select a clock signal, an enable signal, and a local set/reset signal.