Routing signals to pins of components in programmable logic devices
View Patent ↗Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At least two of the signals are routed to a same pin. The method also includes, for each of the signals routed to the same pin, determining a cost value associated with each of two or more pins. the method also includes, for each of the signals routed to the same pin, rerouting the signal to one of the two or more pins having the lowest cost value. The method also includes repeating the determining a cost value and the rerouting until no more than one signal is routed to a pin.
1. A computer-implemented method of routing signals in a programmable logic device (PLD), the method comprising:
routing a plurality of signals to pins of a PLD component configured to perform a logic function, wherein at least two of the plurality of signals are routed to a same component pin;
for each of the signals routed to the same pin:
identifying one or more other component pins that are a logic equivalents to the same pin;
calculating a cost value associated with each of the logic equivalent pins, which include the same pin and the one or more other logic equivalent pins; and
routing the signal to the logic equivalent pin having the lowest cost value; and
reconfiguring the component to perform the logic function in accordance with any change in signal routings to logic equivalent pins.
2. The method of claim 1 , wherein routing the signal to the logic equivalent pin having the lowest cost value includes leaving the signal at the same pin if the same pin has the lowest cost value.
3. The method of claim 1 , wherein the cost value associated with a same pin changes as the number of signals routed to the same pin changes.
4. The method of claim 1 including repeating the identifying, calculating, and routing steps for any signals that are routed to a same pin as a result of an application the method.
5. The method of claim 1 , wherein the cost values are calculated using timing criteria associated with the signals.
6. The method of claim 1 , wherein the cost values are calculated using logic delays associated with the component.
7. The method of claim 1 , wherein the cost values are calculated using congestion values associated with the signals routed to the same pin.
8. A system comprising:
one or more processors; and
one or more memories adapted to store a plurality of computer readable instructions which when executed by the one or more processors are adapted to cause the system to perform a computer-implemented method of routing signals in a programmable logic device (PLD), the method comprising:
routing a plurality of signals to pins of a PLD component configured to perform a logic function, wherein at least two of the plurality of signals are routed to a same component pin;
for each of the signals routed to the same pin:
identifying one or more other component pins that are a logic equivalents to the same pin;
calculating a cost value associated with each of the logic equivalent pins, which include the same pin and the one or more other logic equivalent pins; and
routing the signal to the logic equivalent pin having the lowest cost value; and
reconfiguring the component to perform the logic function in accordance with any change in signal routings to logic equivalent pins.
9. The system of claim 8 , wherein routing the signal to the logic equivalent pin having the lowest cost value includes leaving the signal at the same pin if the same pin has the lowest cost value.
10. The system of claim 8 , wherein the cost value associated with a same pin changes as the number of signals routed to the same pin changes.
11. The system of claim 8 , wherein the method includes repeating the identifying, calculating, and routing steps for any signals that are routed to a same pin as a result of an application the method.
12. The system of claim 8 , wherein the cost values are calculated using timing criteria associated with the signals.
13. The system of claim 8 , wherein the cost values are calculated using logic delays associated with the component.
14. The method of claim 8 , wherein the cost values are calculated using congestion values associated with the signals routed to the same pin.
15. A non-transitory computer readable medium in which are stored computer readable instruction for performing a method of routing signals in a programmable logic device (PLD), the method comprising:
routing a plurality of signals to pins of a PLD component configured to perform a logic function, wherein at least two of the plurality of signals are routed to a same component pin;
for each of the signals routed to the same pin:
identifying one or more other component pins that are a logic equivalents to the same pin;
calculating a cost value associated with each of the logic equivalent pins, which include the same pin and the one or more other logic equivalent pins; and
routing the signal to the logic equivalent pin having the lowest cost value; and
reconfiguring the component to perform the logic function in accordance with any change in signal routings to logic equivalent pins.
16. The computer readable medium of claim 15 , wherein routing the signal to the logic equivalent pin having the lowest cost value includes leaving the signal at the same pin if the same pin has the lowest cost value.
17. The computer readable medium of claim 15 , wherein the cost value associated with a same pin changes as the number of signals routed to the same pin changes.
18. The computer readable medium of claim 15 , wherein the method includes repeating the identifying, calculating, and routing steps for any signals that are routed to a same pin as a result of an application the method.
19. The computer readable medium of claim 15 , wherein the cost values are calculated using timing criteria associated with the signals.
20. The computer readable medium of claim 15 , wherein the cost values are calculated using logic delays associated with the component.