Programmable logic device and method of testing

1. A programmable logic device, comprising:

a plurality of programmable resources;

non-volatile configuration memory adapted to store configuration data for configuring the plurality of programmable resources;

a register adapted to load configuration data into the non-volatile configuration memory; and

test circuitry coupled to the register and adapted to configure a programmable resource with test data stored in the register rather than with configuration data stored in the non-volatile configuration memory.

2. The programmable logic device of claim 1 , wherein the non-volatile configuration memory comprises an array of memory cells and the register comprises a data shift register adapted to load the array.

3. The programmable logic device of claim 1 including a buffer coupled between the configuration memory and a programmable resource, the test circuitry comprising a logic circuit coupled between the register, the configuration memory, and the buffer and responsive to a test mode signal to route test data from the register to the buffer.

4. The programmable logic device of claim 3 , wherein the test circuitry further includes a pull-up/down circuit coupled to the buffer and driven by the logic circuit.

5. The programmable logic device of claim 4 , wherein the pull-up/down circuit is adapted to override data from a non-volatile memory cell to the buffer when driven on by the logic circuit and is further adapted to pass data from the non-volatile memory cell to the buffer when driven off by the logic circuit.

6. The programmable logic device of claim 1 , wherein the non-volatile configuration memory comprises electrically erasable programmable non-volatile memory.

7. A programmable logic device comprising:

a plurality of programmable resources;

non-volatile configuration memory comprising a plurality of memory cells adapted to store configuration data for configuring the plurality of programmable resources;

a buffer coupled between at least one memory cell and a programmable resource;

a register adapted to load configuration data into the non-volatile configuration memory; and

test circuitry coupled to the register and adapted to configure a programmable resource with test data stored in the register rather than with configuration data stored in the non-volatile configuration memory, the test circuitry comprising a logic circuit coupled between the register, the output of the memory cell, and the input of the buffer and responsive to a test mode signal to route test data from the register to the buffer.

8. The programmable logic device of claim 7 , wherein the test circuitry further comprises a pull-up/down circuit coupled to the input of the buffer and driven by the logic circuit.

9. The programmable logic device of claim 8 , wherein the pull-up/down circuit is adapted to override data from a non-volatile memory cell to the buffer when driven on by the logic circuit and is further adapted to pass data from the non-volatile memory cell to the buffer when driven off by the logic circuit.

10. The programmable logic device of claim 7 , wherein the non-volatile configuration memory comprises an array of memory cells and the register comprises a data shift register adapted to load the array.

11. The programmable logic device of claim 7 , wherein the non-volatile configuration memory comprises electrically erasable programmable non-volatile memory.

12. A programmable logic device, comprising:

a plurality of programmable resources;

non-volatile configuration memory adapted to store configuration data for configuring the plurality of programmable resources;

a register adapted to load configuration data into the non-volatile configuration memory; and

means for configuring a programmable resource with test data stored in the register rather than with configuration data stored in the non-volatile configuration memory.