Variable response mode for synchronous data read
View Patent ↗In one embodiment, a programmable logic device includes a memory and an input/output (I/O) interface adapted to enter a variable response mode responsive to an assertion of a control signal. The I/O interface is operable in the variable response mode to respond to a read command from an external device by retrieving data from the memory and to shift dummy data to the external device until an internal data ready signal is asserted.
1. A programmable logic device, comprising:
a memory;
an input/output (I/O) interface adapted to respond to a read command received from an external device by retrieving data from the memory, wherein the I/O interface is further adapted to monitor an internal data ready signal asserted by the programmable logic device and to shift out dummy data to the external device from the receiving of the read command until the internal data ready signal is asserted; and
a control register operable to store a control bit signal that enables the I/O interface to monitor the internal data ready signal.
2. The programmable logic device of claim 1 , wherein the I/O interface is further adapted to shift out the retrieved data to the external device after the data ready signal is asserted.
3. The programmable logic device of claim 2 , wherein the I/O interface is further adapted to shift out an external data ready signal to the external device before shifting out the retrieved data.
4. The programmable logic device of claim 3 , wherein the external data ready signal is a one-byte signal.
5. The programmable logic device of claim 1 , wherein the memory is a flash memory.
6. The programmable logic device of claim 1 , wherein the memory is an embedded memory.
7. The programmable logic device of claim 1 , wherein the programmable logic device is a field programmable gate array (FPGA).
8. A method, comprising:
receiving a read command from an external device at a programmable logic device's input/output (I/O) interface, wherein the read command commands the I/O interface to retrieve data from a memory in the programmable logic device;
monitoring an internal data ready signal from a control bit signal stored in a control register within the programmable logic device, the internal data ready signal being asserted by the programmable logic device after the data is retrieved from the memory;
after receiving the read command and before the internal data ready signal is asserted, shifting dummy data out of the I/O interface to the external device; and
after the internal data ready signal is asserted, shifting the retrieved data out of the I/O interface to the external device.
9. The method of claim 8 , further comprising shifting an external data ready signal out of the I/O interface to the external device before shifting the retrieved data.
10. The method of claim 8 , wherein the programmable logic device is a field programmable gate array (FPGA).
11. The method of claim 8 , wherein the I/O interface is a SPI interface.
12. The method of claim 8 , wherein the external device is a host processor having a master SPI interface and the I/O interface is a slave SPI interface.
13. A logic device, comprising:
a memory;
an input/output (I/O) interface adapted to respond to a read command received from an external device by retrieving data from the memory, wherein the I/O interface is further adapted to monitor an internal data ready signal asserted by the logic device and to shift out dummy data to the external device from the receiving of the read command until the internal data ready signal is asserted; and
a control register operable to store a control bit signal that enables the I/O interface to monitor the internal data ready signal.
14. The logic device of claim 13 , wherein the I/O interface is further adapted to shift out the retrieved data to the external device after the data ready signal is asserted.
15. The logic device of claim 14 , wherein the I/O interface is further adapted to shift out an external data ready signal to the external device before shifting out the retrieved data.
16. The logic device of claim 15 , wherein the external data ready signal is a one-byte signal.
17. The logic device of claim 13 , wherein the memory is a flash memory.
18. The logic device of claim 13 , wherein the memory is an embedded memory.
19. The logic device of claim 13 , wherein the I/O interface is a SPI interface.