Separate configuration of I/O cells and logic core in a programmable logic device

1. A programmable logic device (PLD), comprising:

a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logic blocks;

a plurality of input/output (I/O cells), each I/O cell associating with a corresponding set of I/O configuration memory cells;

a plurality of boundary scan cells corresponding to the plurality of I/O cells, the boundary scan cells being configurable to form a second configuration data shift register for the I/O configuration memory cells;

a plurality of switches between each I/O cell's boundary scan cell and the associated I/O configuration memory cells; and

a plurality of address lines coupled to the plurality of switches.

2. The PLD of claim 1 , wherein each boundary scan cell includes a JTAG BC7 cell.

3. The PLD of claim 1 , wherein each boundary scan cell includes a JTAG BC1 cell.

4. The PLD of claim 1 , wherein the PLD comprises a field programmable gate array (FPGA).

5. The PLD of claim 1 , wherein the switches comprise field effect transistors (FETs).

6. The PLD of claim 1 , wherein the configuration memory cells comprise SRAM cells, the PLD further comprising:

a plurality of sense amplifiers for sensing the plurality of SRAM cells.

7. A programmable logic device (PLD), comprising:

a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logic blocks;

a plurality of input/output (I/O cells), each I/O cell associating with a corresponding set of I/O configuration memory cells; and

a plurality of boundary scan cells corresponding to the plurality of I/O cells, the boundary scan cells being configurable to form a second configuration data shift register for the I/O configuration memory cells,

wherein each boundary scan cell includes:

a data register clocked by a clock DR signal so as to store a bit from the configuration data; and

an update register triggered to store a data signal from the data register responsive to a processing of a boundary scan updateDR signal and a configuration mode signal such that the update register is not triggered to store the data signal during a configuration mode, and wherein the data signal is coupled to a corresponding I/O ring configuration memory cell during the configuration mode.

8. The PLD of claim 7 , wherein each boundary scan cell further includes an AND gate to process the boundary scan updateDR signal and the configuration mode signal.

9. A programmable logic device (PLD), comprising:

a plurality of input/output (I/O cells), each I/O cell associated with a corresponding set of I/O configuration memory cells;

a plurality of boundary scan cells corresponding to the plurality of I/O cells, each boundary scan cell including a data register;

a plurality of switches coupled between the data registers of the boundary scan cells and the associated I/O configuration memory cells; and

a plurality of address lines coupled to the plurality of switches,

wherein the boundary scan cells are configurable to form a configuration data shift register for shifting configuration data into the I/O configuration memory cells from the data registers of the boundary scan cells in response to address signals on the address lines coupled to the switches.

10. The PLD of claim 9 , wherein the switches comprise field effect transistors (FETs).

11. The PLD of claim 9 , wherein the configuration memory cells comprise SRAM cells, the PLD including a plurality of sense amplifiers for sensing the plurality of SRAM cells.

12. The PLD of claim 9 , wherein the PLD comprises a field programmable gate array (FPGA).