Clock systems and methods
View Patent ↗Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and a multi-bit control signal. A clock skew circuit provides a delay to the clock signal based on the delay control signal provided by the control signal. Memory coupled to the control logic provides the multi-bit control signal.
1. A clock skew control circuit for an integrated circuit comprising:
a course skew circuit adapted to receive a clock signal from a clock generator and provide the clock signal with a first delay;
a first multiplexer adapted to select the clock signal from the clock generator or the delayed clock signal from the coarse skew circuit to provide as the clock signal;
a fine skew circuit adapted to receive the clock signal from the first multiplexer and provide the clock signal with a second delay, wherein the delay provided by the fine skew circuit is based at least in part on a bias signal provided by the clock generator;
a second multiplexer adapted to select between the clock signal from the first multiplexer and the delayed clock signal from the fine skew circuit, and
memory coupled to the first and second multiplexers for providing control signals that control clock signal selection by the multiplexers.
2. The clock skew control circuit of claim 1 , wherein the memory is non-volatile memory.
3. The clock skew control circuit of claim 1 , wherein the integrated circuit includes the clock generator.
4. The clock skew circuit of claim 3 , wherein the clock generator includes a phase-locked loop.
5. The clock skew control circuit of claim 1 including a current-controlled digital-to-analog converter adapted to receive the bias signal and digital control signals and provide a current-based delay control signal to the fine skew circuit to determine the delay provided by the fine skew circuit.
6. The clock skew control circuit of claim 5 including memory coupled to the current-controlled digital-to-analog converter for providing the digital control signals.
7. An integrated circuit comprising:
a clock generator adapted to provide a bias signal and a clock signal;
a coarse skew circuit adapted to receive the clock signal from the clock generator and provide the clock signal with a first delay;
a first multiplexer adapted to select the clock signal from the clock generator or the delayed clock signal from the coarse skew circuit to provide as the clock signal;
a current-controlled digital to analog converter adapted to receive the bias signal and a digital control signal and provide a current-based delay control signal;
a fine skew circuit adapted to provide a second delay to the clock signal received from the multiplexer based on the bias signal and the current-based delay control signal provided by the digital-to-analog converter; and
memory coupled to the current-controlled digital-to-analog converter for providing the digital control signal.
8. The integrated circuit of claim 7 including a second multiplexer adapted to select between the clock signal received from the first multiplexer and the delayed clock signal from the fine skew circuit.
9. The integrated circuit of claim 7 , wherein the clock generator is a phase-locked loop and the bias signal is a VCO bias signal.
10. An integrated circuit comprising:
a clock generator adapted to provide a bias signal and a clock signal;
control logic adapted to receive the bias signal and a multi-bit control signal and provide a delay control signal based on the bias signal and multi-bit control signal;
a course skew circuit adapted to receive a clock signal from a clock generator and provide the clock signal with a first delay;
a first multiplexer adapted to select the clock signal from the clock generator or the delayed clock signal from the coarse skew circuit to provide as the clock signal;
a fine skew circuit adapted to provide a second delay to the clock signal selected by the multiplexer, the delay based on the delay control signal provided by the control logic; and
memory coupled to the control logic for providing the multi-bit control signal.
11. The integrated circuit of claim 10 including a second multiplexer adapted to select between the clock signal from the first multiplexer and the delayed clock signal from the fine skew circuit.
12. The integrated circuit of claim 10 , wherein the control logic includes a digital-to-analog converter adapted to receive the bias signal and digital control signals and provide a current-based delay control signal to the fine skew circuit to determine the delay provided by the fine skew circuit.
13. The integrated circuit of claim of claim 12 including memory coupled to the digital-to-analog converter for providing the digital control signals.
14. The integrated circuit of claim 10 , wherein the clock generator is a phase-locked loop and the bias signal is a VCO bias signal.