Oscillator tuning for phase-locked loop circuit

1. A method of tuning an oscillator of a phase-locked loop (PLL) circuit, the method comprising:

adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator;

adjusting a fine control signal to select a position on the selected frequency tuning curve, wherein a frequency of the oscillator is determined by the coarse control signal and the fine control signal;

attempting to detect a lock between a feedback signal and a reference signal, wherein a frequency of the feedback signal is determined by the frequency of the oscillator;

comparing the fine control signal to a reference value if the lock is detected;

adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range; and

permitting the frequency of the oscillator to settle before the coarse control signal is adjusted,

wherein the frequency of the oscillator is further determined by:

comparing the reference signal with the feedback signal;

increasing the frequency of the oscillator if the frequency of the feedback signal is less than the frequency of the reference signal; and

decreasing the frequency of the oscillator if the frequency of the feedback signal is greater than the frequency of the reference.

2. The method of claim 1 , further comprising adjusting the fine control signal to select a different position on the selected frequency tuning curve if the selected position on the selected frequency tuning curve is within the desired tuning range and the lock between the feedback signal and the reference signal is lost.

3. The method of claim 1 , further comprising adjusting the coarse control signal to select a different one of the frequency tuning curves if the lock is not detected.

4. The method of claim 1 , wherein the frequency of the oscillator is further determined by:

repeating the comparing to perform a desired number of iterations;

setting a first flag and increasing the frequency of the oscillator if the frequency of the feedback signal is less than the frequency of the reference signal for all of the iterations; and

setting a second flag and decreasing the frequency of the oscillator if the frequency of the feedback signal is greater than the frequency of the reference signal for all of the iterations.

5. The method of claim 4 , wherein the adjusting the fine control signal is performed only if both of the first and second flags are set.

6. The method of claim 5 , wherein the adjusting a coarse control signal comprises:

setting a counter to a preset value; and

during each iteration, selectively increasing or decreasing a current value of the counter based on whether the frequency of the feedback signal is higher or lower than the frequency of the reference signal, wherein the first and second flags are set using the current value of the counter.

7. The method of claim 1 , wherein the adjusting a coarse control signal comprises:

providing a digital coarse tuning value using a state machine;

converting the digital coarse tuning value to an analog coarse control signal; and

providing the analog coarse control signal to the oscillator.

8. The method of claim 1 , further comprising maintaining the fine control signal at a minimum value while the coarse control signal is adjusted.

9. A phase-locked loop (PLL) circuit comprising:

an oscillator adapted to receive a coarse control signal and a fine control signal wherein a frequency of the oscillator is determined by the coarse control signal and the fine control signal;

a state machine adapted to adjust the coarse control signal to select one of a plurality of frequency tuning curves of the oscillator;

a tuning loop adapted to adjust the fine control signal to select a position on the selected frequency tuning curve;

a lock detector adapted to attempt to detect a lock between a feedback signal and a reference signal, wherein a frequency of the feedback signal is determined by the frequency of the oscillator;

a comparator adapted to compare the fine control signal to a reference value if the lock is detected; and

wherein the state machine is adapted to:

adjust the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range;

increase the frequency of the oscillator if the frequency of the feedback signal is less than the frequency of the reference signal; and

decrease the frequency of the oscillator if the frequency of the feedback signal is greater than the frequency of the reference signal.

10. The PLL circuit of claim 9 , wherein the tuning loop is adapted to adjust the fine control signal to select a different position on the selected frequency tuning curve if the selected position on the selected frequency tuning curve is within the desired tuning range and the lock between the feedback signal and the reference signal is lost.

11. The PLL circuit of claim 9 , wherein the state machine is adapted to adjust the coarse control signal to select a different one of the frequency tuning curves if the lock is not detected.

12. The PLL circuit of claim 9 , wherein the comparator is a first comparator, the PLL circuit further comprising:

a second comparator adapted to compare the reference signal with the feedback signal for a desired number of iterations;

wherein the state machine is adapted to set a first flag and increase the frequency of the oscillator if the frequency of the feedback signal is less than the frequency of the reference signal for all of the iterations; and

wherein the state machine is adapted to set a second flag and decrease the frequency of the oscillator if the frequency of the feedback signal is greater than the frequency of the reference signal for all of the iterations.

13. The PLL circuit of claim 12 , wherein the state machine is adapted to prevent the tuning loop from adjusting the fine control signal unless both of the first and second flags are set.

14. The PLL circuit of claim 13 , wherein the state machine is adapted to:

set a counter to a preset value; and

during each iteration, selectively increase or decrease a current value of the counter based on whether the frequency of the feedback signal is higher or lower than the frequency of the reference signal, wherein the first and second flags are set using the current value of the counter.

15. The PLL circuit of claim 9 , wherein the coarse control signal is an analog coarse control signal, the PLL circuit further comprising a digital-to-analog converter (DAC) adapted to receive a digital coarse tuning value from the state machine and convert the digital coarse tuning value to the analog coarse control signal.

16. The PLL circuit of claim 9 , wherein the state machine is adapted to wait for the frequency of the oscillator to settle before adjusting the coarse control signal.

17. The PLL circuit of claim 9 , further comprising a switch adapted to maintain the fine control signal at a minimum value while the coarse control signal is adjusted.

18. A phase-locked loop (PLL) circuit comprising:

an oscillator;

means for adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator;

means for adjusting a fine control signal to select a position on the selected frequency tuning curve, wherein a frequency of the oscillator is determined by the coarse control signal and the fine control signal;

means for attempting to detect a lock between a feedback signal and a reference signal, wherein a frequency of the feedback signal is determined by the frequency of the oscillator;

means for comparing the fine control signal to a reference value if the lock is detected;

means for adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range;

means for adjusting the fine control signal to select a different position on the selected frequency tuning curve if the selected position on the selected frequency tuning curve is within the desired tuning range and the lock between the feedback signal and the reference signal is lost; and

means for increasing the frequency of the oscillator if the frequency of the feedback signal is less than the frequency of the reference signal and for decreasing the frequency of the oscillator if the frequency of the feedback signal is greater than the frequency of the reference signal.