Alignment circuit for parallel data streams

1. A receiver (e.g., 100 ) comprising:

serial-to-parallel (S-to-P) conversion circuitry (e.g., 110 , 130 ) configured to convert a serial input data stream (e.g., 105 ) having M-bit serial-data words into an N-bit parallel data stream (e.g., 137 ), wherein M and N are positive integers; and

continuous alignment circuitry (e.g., 150 ) configured to correct for misalignment of the M-bit serial-data words within the N-bit parallel data stream to generate an N-bit aligned parallel output data stream (e.g., 175 ), wherein the continuous alignment circuitry is based on a mapping (e.g., Table I) from each of a finite number of possible previous alignment conditions (e.g., A, B, C, D) to a corresponding finite number of possible subsequent alignment conditions (e.g., B, C, D, E, F, G).

2. The invention of claim 1 , wherein the receiver further comprises initialization alignment circuitry (e.g., 140 ) configured to establish an initial alignment condition for the N-bit parallel data stream that dictates each of the finite number of possible previous alignment conditions and the corresponding finite number of possible subsequent alignment conditions.

3. The invention of claim 2 , wherein the initialization alignment circuitry comprises:

a barrel shifter (e.g., 144 ) configured to selectively adjust misalignment of the N-bit parallel data stream (e.g., 137 ) based on a specified shift value (e.g., 0-7 bytes) to generate a selectively adjusted N-bit parallel data stream (e.g., 145 ); and

a detector (e.g., 142 ) configured to detect the misalignment in the N-bit parallel data stream (e.g., 137 ) and generate the specified shift value for the barrel shifter.

4. The invention of claim 2 , wherein:

M=32 and N=64;

the 64-bit parallel data stream comprises two 32-bit parallel-data words;

the initial alignment condition established by the initialization alignment circuitry corresponds to the 32-bit serial-data words aligned with the two 32-bit parallel-data words in the 64-bit parallel data stream; and

according to the mapping, each possible previous alignment condition maps to two possible subsequent alignment conditions that are 16 bits away from the possible previous alignment condition.

5. The invention of claim 1 , wherein the misalignment results from clock tolerance compensation (CTC) processing (e.g., 114 ) upstream of the continuous alignment circuitry.

6. The invention of claim 5 , wherein the CTC processing selectively inserts or removes a P-bit Idle word into and from the N-bit parallel data stream, wherein P is different from M.

7. The invention of claim 1 , wherein the continuous alignment circuitry comprises:

a plurality of registers (e.g., 152 , 154 ) configured to store a plurality of consecutive N-bit parallel data words;

a plurality of overlapping multiplexers (e.g., 156 ( 1 )-( 4 )), each configured to generate a different, overlapping, N-bit parallel data word from the consecutive N-bit parallel data words stored in the plurality of registers;

a selection multiplexer (e.g., 158 ) configured to receive the plurality of overlapping, N-bit parallel data words from the plurality of overlapping multiplexers and selectively output one of the overlapping, N-bit parallel data words; and

a processor (e.g., 160 ) configured to generate a mux select signal (e.g., 161 ) to control the selection by the selection multiplexer based on a previous value for the mux select signal.

8. The invention of claim 7 , wherein the processor (i) detects a change in position of start-of-packet (SOP) or start-of-control-symbol (SOC) data in the plurality of consecutive N-bit parallel data words stored in the plurality of registers and (ii) generates the mux select signal further based on the detected change in position.

9. The invention of claim 7 , wherein the continuous alignment circuitry further comprises an output multiplexer (e.g., 166 ) configured to receive the selected, overlapping, N-bit parallel data word (e.g., 159 ) from the selection multiplexer and selectively overwrite a portion of the bits in the selected, overlapping, N-bit parallel data word to generate an N-bit word for the N-bit aligned parallel output data stream.

10. The invention of claim 7 , wherein:

M=32 and N=64;

the 64-bit parallel data stream comprises two 32-bit parallel-data words;

according to the mapping, each possible previous alignment condition maps to two possible subsequent alignment conditions that are 16 bits away from the possible previous alignment condition;

the plurality of registers are two 64-bit registers (e.g., 152 , 154 ) configured to store two consecutive 64-bit parallel data words;

the plurality of overlapping multiplexers are four overlapping multiplexers (e.g., 156 ( 1 )-( 4 )), each configured to generate a different, overlapping, 64-bit parallel data word from two registers; and

the selection multiplexer (e.g., 158 ) is configured to receive the four overlapping, N-bit parallel data words from the four overlapping multiplexers and selectively output one of the overlapping, N-bit parallel data words.

11. The invention of claim 1 , wherein the S-to-P conversion circuitry and the continuous alignment circuitry are implemented on a field-programmable gate array (FPGA).

12. A method comprising:

(a) converting (e.g., 110 , 130 ) a serial input data stream (e.g., 105 ) having M-bit serial-data words into an N-bit parallel data stream (e.g., 137 ), wherein M and N are positive integers; and

(b) correcting (e.g., 150 ) for misalignment of the M-bit serial-data words within the N-bit parallel data stream to generate an N-bit aligned parallel output data stream (e.g., 175 ), wherein the correcting is based on a mapping (e.g., Table I) from each of a finite number of possible previous alignment conditions (e.g., A, B, C, D) to a corresponding finite number of possible subsequent alignment conditions (e.g., B, C, D, E, F, G).