Compression and decompression of configuration data using repeated data frames
In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data frame comprises a first data set; embedding a first instruction into the compressed bitstream to load the first data frame into a first row of configuration memory of the PLD at an address associated with the first data frame; identifying a second data frame in the uncompressed bitstream, wherein the second data frame comprises the first data set; and embedding a second instruction into the compressed bitstream to load the first data frame into a second row of the configuration memory at an address associated with the second data frame.
1. A method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD), the method comprising:
embedding a first data frame from the uncompressed bitstream into the compressed bitstream;
embedding a first instruction into the compressed bitstream to load the first data frame into a data shift register;
embedding a second instruction into the compressed bitstream to load a first address associated with the first data frame into an address shift register; and
embedding a third instruction into the compressed bitstream to load a second address associated with a second data frame into the address shift register, wherein the second data frame is an instance of the first data frame.
2. The method of claim 1 including passing the compressed bitstream to the PLD.
3. The method of claim 1 including:
embedding a third data frame into the compressed bitstream, wherein the third data frame is not an instance of the first data frame;
embedding a fourth instruction into the compressed bitstream to load the third data frame into the data shift register; and
embedding a fifth instruction into the compressed bitstream to load a third address associated with the third data frame into the address shift register.
4. The method of claim 3 including:
embedding a sixth instruction into the compressed bitstream to load a fourth address associated with a fourth data frame into the address shift register, wherein the fourth data frame is an instance of the third data frame.
5. A non-transitory computer-readable medium on which is stored a computer program that performs a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD), the method comprising:
embedding a first data frame from the uncompressed bitstream into the compressed bitstream;
embedding a first instruction into the compressed bitstream to load the first data frame into a data shift register;
embedding a second instruction into the compressed bitstream to load a first address associated with the first data frame into an address shift register; and
embedding a third instruction into the compressed bitstream to load a second address associated with a second data frame into the address shift register, wherein the second data frame is an instance of the first data frame.
6. A method of configuring a programmable logic device (PLD) with a compressed bitstream, the method comprising:
reading a first data frame embedded in the compressed bitstream;
executing a first instruction embedded in the compressed bitstream to load the first data frame into a data shift register;
executing a second instruction embedded in the compressed bitstream to load a first address associated with the first data frame into an address shift register; and
executing a third instruction embedded in the compressed bitstream to load a second address associated with a second data frame into the address shift register, wherein the second data frame is an instance of the first data frame.
7. The method of claim 6 including:
reading a third data frame embedded in the compressed bitstream, wherein the third data frame is not an instance of the first data frame;
executing a fourth instruction embedded in the compressed bitstream to load the third data frame into the data shift register; and
executing a fifth instruction embedded in the compressed bitstream to load a third address associated with the third data frame into the address shift register.
8. The method of claim 7 including:
executing a sixth instruction embedded in the compressed bitstream to load a fourth address associated with a fourth data frame into the address shift register, wherein the fourth data frame is an instance of the third data frame.
9. The method of claim 6 including receiving the compressed bitstream at a data port of the PLD from a computing device external to the PLD.
10. The method of claim 6 including receiving the compressed bitstream at a data port of the PLD from a memory external to the PLD.
11. A programmable logic device (PLD) comprising:
configuration memory; and
a configuration download engine adapted to:
read a first data frame embedded in a compressed bitstream received by the PLD;
execute a first instruction embedded in the compressed bitstream to load the first data frame into a data shift register;
execute a second instruction embedded in the compressed bitstream to load a first address associated with the first data frame into an address shift register; and
execute a third instruction embedded in the compressed bitstream to load a second address associated with a second data frame into the address shift register, wherein the second data frame is an instance of the first data frame.
12. The PLD of claim 11 , wherein the configuration download engine is further adapted to:
read a third data frame embedded in the compressed bitstream, wherein the third data frame is not an instance of the first data frame;
execute a fourth instruction embedded in the compressed bitstream to load the third data frame into the data shift register; and
execute a fifth instruction embedded in the compressed bitstream to load a third address associated with the third data frame into the address shift register.
13. The PLD of claim 12 , wherein the configuration download engine is further adapted to:
execute a sixth instruction embedded in the compressed bitstream to load a fourth address associated with a fourth data frame into the address shift register, wherein the fourth data frame is an instance of the third data frame.
14. A compressed configuration bitstream for a programmable logic device (PLD) comprising:
a first data frame;
a first embedded instruction to load the first data frame into a data shift register;
a second embedded instruction to load a first address associated with the first data frame into an address shift register; and
a third embedded instruction to load a second address associated with a second data frame into the address shift register, wherein the second data frame is an instance of the first data frame.
15. The compressed configuration bitstream of claim 14 including:
a third data frame, wherein is not an instance of the first data frame; and
a third instruction to load the third data frame into a third row of the configuration memory at an address associated with the third data frame
a fourth embedded instruction to load the third data frame into the data shift register; and
a fifth embedded instruction to load a third address associated with the third data frame into the address shift register.
16. The compressed configuration bitstream of claim 15 including:
a sixth embedded instruction to load a fourth address associated with a fourth data frame into the address shift register, wherein the fourth data frame is an instance of the third data frame.