Register data retention systems and methods during reprogramming of programmable logic devices
View Patent ↗Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.
1. A programmable logic device comprising:
a plurality of logic blocks, the logic blocks adapted to generate user data during operation of the programmable logic device;
a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and
configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers before the reprogramming operation and a reprogrammed data path between the logic blocks and the registers after the reprogramming operation.
2. The programmable logic device of claim 1 including a logic circuit adapted to control transfer of the user data from the logic blocks to the registers via the routing resources.
3. The programmable logic device of claim 2 , wherein the routing resources comprise common interface blocks, and wherein the logic circuit controls the registers to receive the user data from the common interface blocks prior to the reprogramming operation.
4. The programmable logic device of claim 2 , wherein the logic circuit is further adapted to maintain the user data transferred to the registers during the reprogramming operation.
5. The programmable logic device of claim 1 , further comprising:
a volatile memory block adapted to receive and store data during operation of the programmable logic device;
input/output blocks adapted to transfer data into and out of the programmable logic device; and
wherein the routing resources are further adapted to provide a programmed data path between the volatile memory block, the input/output blocks, the logic blocks, and the registers.
6. A method of retaining user data during reprogramming of a programmable logic device having programmable logic and configurable routing resources, the method comprising:
transferring user data from the programmable logic to storage registers within the programmable logic device via a programmed data path of the routing resources;
reprogramming the programmable logic device, including providing as part of the reprogramming a reprogrammed data path between the programmable logic and the storage registers;
storing the user data in the storage registers during reprogramming of the programmable logic device; and
transferring the user data from the storage registers via the reprogrammed data path to the programmable logic after the reprogramming of the programmable logic device.
7. The method of claim 6 , wherein the programmable logic comprises logic blocks and at least one memory block.
8. The method of claim 6 , wherein the programmed data path and the reprogrammed data path each comprises a parallel data path.
9. The programmable logic device of claim 1 , wherein the programmed data path and the reprogrammed data path each comprises a parallel data path.