Input/output placement systems and methods to reduce simultaneous switching output noise
View Patent ↗Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.
1. A computer-method of performing input/output (I/O) signal placement to pins of an electronic device, the method comprising:
in a software design tool executing on a computer:
placing all pre-assigned I/O signals to their assigned pin locations;
placing unassigned I/O signals to initial I/O pin locations; and
performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements through an SSO cost function,
wherein a probability of an I/O signal placement being moved from an initial I/O pin location is p=e −ΔC/T , where ΔC represents an increase in the SSO cost function and T represents temperature.
2. The method of claim 1 , wherein the placing unassigned I/O signals to initial I/O pin locations is based on I/O banking rules.
3. The method of claim 1 , wherein the performing of the simulated annealing is based on I/O banking rules and an SSO cost function.
4. The method of claim 1 , wherein SSO noise calculations are performed based on a table lookup and/or a formula for the performing for comparison to the SSO noise requirements, and wherein the SSO noise calculations take into account die pin location, packaging, and/or one or more virtual signals.
5. The method of claim 1 , wherein the performing the simulated annealing is repeated to eliminate SSO noise violations, with SSO noise calculations for the simulated annealing based on structured SSO noise data.
6. The method of claim 1 , further comprising performing a second simulated annealing for timing and/or area goals.
7. The method of claim 1 , further comprising performing a second simulated annealing for timing and/or area goals, wherein the second simulated annealing is further based on I/O banking rules and SSO noise I/O rules.
8. The method of claim 1 , wherein the simulated annealing further accounts for I/O banking rules, timing goals, and/or area goals.
9. The method of claim 1 , wherein the method is performed as part of a programmable logic device design tool, with the SSO noise data provided along with floor planning information.
10. The method of claim 1 , further comprising:
receiving hardware data on SSO noise conditions;
generating additional data based on the hardware data; and
providing the hardware data and the additional data for SSO noise calculations which are performed during the simulated annealing.
11. The method of claim 10 , further comprising:
storing the hardware data and the additional data in data tables, which are structured for the SSO noise calculations, and wherein the generating of at least a portion of the additional data is performed using computer simulations.
12. A non-transitory computer-readable medium on which is stored a computer program that when executed by a computer performs a method of input/output (I/O) signal placement to pins of an electronic device, the method comprising:
placing all pre-assigned I/O signals to their assigned pin locations;
placing unassigned I/O signals to initial I/O pin locations; and
performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements through an SSO cost function,
wherein a probability of an I/O signal placement being moved from an initial I/O pin location is p=e −ΔC/T , where ΔC represents an increase in the SSO cost function and T represents temperature.
13. The method of claim 12 , wherein the performing of the simulated annealing is based on I/O banking rules and an SSO cost function.
14. The method of claim 12 , wherein SSO noise calculations are performed based on a table lookup and/or a formula for the performing for comparison to the SSO noise requirements, and wherein the SSO noise calculations takes into account die pin location, packaging, and/or one or more virtual signals.
15. The method of claim 12 , wherein the performing the simulated annealing is repeated to eliminate SSO noise violations, with SSO noise calculations for the simulated annealing based on structured SSO noise data.
16. The method of claim 12 , further comprising performing a second simulated annealing for timing and/or area goals.
17. The method of claim 12 , further comprising performing a second simulated annealing for timing and/or area goals, wherein the second simulated annealing is further based on I/O banking rules and SSO noise I/O rules.
18. The method of claim 12 , wherein the simulated annealing further accounts for I/O banking rules, timing goals, and/or area goals.
19. The method of claim 12 , wherein the method is performed as part of a programmable logic device design tool, with the SSO noise data provided along with floor planning information.