Granted Patent
Utility
US 6,486,705
· Confirmation No. 1229
SIGNAL DISTRIBUTION SCHEME IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) OR FIELD PROGRAMMABLE SYSTEM CHIP (FPSC) INCLUDING CYCLE STEALING UNITS
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2019-05-21 | OATH |
Oath or Declaration filed | 131 | View | |
| 2001-05-25 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-05-25 | SPEC |
Specification | 12 | View | |
| 2001-05-25 | CLM |
Claims | 3 | View | |
| 2001-05-25 | ABST |
Abstract | 1 | View | |
| 2001-05-25 | DRW |
Drawings-only black and white line drawings | 4 | View |
Inventors
William B. Andrews
Long Pond, PA
Alfred E. Dunlop
Murray Hill, NJ
John P. Fishburn
Murray Hill, NJ
Harold N. Scholz
Allentwon, PA
Attorneys & Agents of Record
Classification
USPC
326/93
Prosecution
Publication
- Pub. No.
- US20020003445A1
- Pub. Date
- 2002-01-10
Patent Term Adjustment
-38days
RELEASE OF SECURITY INTEREST
Recorded 2019-05-21
SECURITY INTEREST
Recorded 2019-05-21
SECURITY INTEREST
Recorded 2015-03-19
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-06-18
from
AGERE SYSTEMS INC.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-02-20
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-08-29
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