Patent Assignment
Reel/Frame 035225/0839
Security Interest
Recorded: 2015-03-19
Pages: 82
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(56)
Finite State Machine with Associated Memory
Patent:
6,628,660 →
Application:
09/330,753 →
Zero-Power Cmos Non Volatile Memory Cell Having an Avalanche Injection Element
Patent:
6,028,789 →
Application:
09/334,051 →
Non-Volatile Memory Cell Having Dual Avalanche Injection Elements
Patent:
6,034,893 →
Application:
09/334,052 →
Integrated Circuit with Standard Cell Logic and Spare Gates
Patent:
6,404,226 →
Application:
09/400,029 →
On-Line Testing of the Programmable Logic Blocks in Field Programmable Gate Arrays
Patent:
6,550,030 →
Application:
09/405,958 →
On-Line Testing of the Programmable Interconnect Network in Field Programmable Gate Arrays
Patent:
6,574,761 →
Application:
09/406,219 →
Combination of Global Clock and Localized Clocks
Patent:
6,191,609 →
Application:
09/433,642 →
Method for Minimizing Instantaneous Currents When Driving Bus Signals
Patent:
6,278,311 →
Application:
09/440,207 →
Programmable Logic Device
Patent:
6,294,925 →
Application:
09/440,460 →
Method of Operating Eeprom Memory Cells Having Transistors with Thin Gate Oxide and Reduced Disturb
Patent:
6,208,559 →
Application:
09/441,220 →
Method for in-System Programming of Serially Configured Eeproms Using a Jtag Interface of a Field Programmable Gate Array
Patent:
6,137,738 →
Application:
09/452,017 →
Inversion of Product Term Line Before or Logic in a Programmable Logic Device (Pld)
Patent:
6,326,808 →
Application:
09/454,322 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,150,842 →
Application:
09/472,645 →
Amplifier having an adjust resistor network
Patent:
6,362,684 →
Application:
09/506,180 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Patent:
6,424,209 →
Application:
09/507,580 →
Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5volt)semiconductor process
Patent:
6,351,157 →
Application:
09/548,171 →
Decoded generic routing pool
Patent:
6,288,937 →
Application:
09/567,898 →
Complementary Avalanche Injection Eeprom Cell
Patent:
6,570,212 →
Application:
09/578,086 →
Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources
Patent:
6,292,930 →
Application:
09/603,119 →
An Fpga Device and Method That Includes a Variable Grain Function Architecture for Implementing Configuration Logic Blocks and a Complimentary Variable Length Interconnect Architecture for Providing Configurable Routing Between Configuration Logic Blocks
Patent:
6,216,257 →
Application:
09/603,807 →
On-Line Fault Tolerant Operation via Incremental Reconfiguration of Field Programmable Gate Arrays
Patent:
6,530,049 →
Application:
09/611,449 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,380,759 →
Application:
09/626,094 →
Configurable Logic Array Incuding Lookup Table Means for Generating Functions of Different Numbers of Input Terms
Patent:
6,567,969 →
Application:
09/632,319 →
Compact Single-Poly Two-Transistor Eeprom Cell
Patent:
6,627,947 →
Application:
09/643,279 →
High Speed Schmitt Trigger with Low Supply Voltage
Patent:
6,433,602 →
Application:
09/651,689 →
Process for Manufacturing Shallow Trenches Filled with Dielectric Material Having Low Mechanical Stress
Patent:
6,455,912 →
Application:
09/651,805 →
High voltage CMOS switch
Patent:
6,370,071 →
Application:
09/660,707 →
Programmable Logic Device
Patent:
6,462,576 →
Application:
09/661,585 →
Double Differential Comparator and Programmable Analog Block Architecture Using Same
Patent:
6,701,340 →
Application:
09/668,896 →
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
Patent:
6,249,144 →
Application:
09/669,186 →
On-Line Testing of Field Programmable Gate Array Resources
Patent:
6,631,487 →
Application:
09/671,853 →
Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in Fpga Device
Patent:
6,470,485 →
Application:
09/692,694 →
Wide Input Programmable Logic System and Method
Patent:
6,507,212 →
Application:
09/704,487 →
Method and structure dynamic in-system programming
Patent:
6,356,107 →
Application:
09/712,000 →
Scalable architecture for high density cPLD's having two-level hierarchy of routing resources
Patent:
6,348,813 →
Application:
09/721,153 →
Combination of Bpteos Oxide Film with Cmp and Rta to Achieve Good Data Retention
Method for Forming a Semiconductor Device Using Lpcvd Nitride to Protect Floating Gate from Charge Loss
Patent:
6,287,916 →
Application:
09/731,185 →
Programmable Power Management System and Method
Methods for Configuring Fpga's Having Variable Grain Blocks and Shared Logic for Providing Symmetric Routing of Result Output to Differently-Directed and Tristateable Interconnect Resources
Voltage Level Translator Systems and Methods
Sense Amplifier Systems and Methods
Patent:
6,414,521 →
Application:
09/775,489 →
Programming Programmable Logic Devices Using Hidden Switches
Methods for Configuring Fpga ' S Having Variable Grain Components for Providing Time-Shared Access to Interconnect Resources
Clock Signal Selection System, Method of Generating a Clock Signal and Programmable Clock Manager Including Same
Signal Distribution Scheme in Field Programmable Gate Array (Fpga) or Field Programmable System Chip (Fpsc) Including Cycle Stealing Units
Multi-Master Multi-Slave System Bus in a Field Programmable Gate Array (Fpga)
Double Data Rate Input and Output in a Programmable Logic Device
Multi-Functional I/O Buffers in a Field Programmable Gate Array (Fpga)
Field Programmable Gate Array (Fpga) Bit Stream Format
Eeprom Tunnel Window for Program Injection via P+ Contacted Inversion
Patent:
6,455,375 →
Application:
09/870,541 →
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,498,538 →
Application:
09/870,877 →
Low Voltage, High Speed Cmos Cml Latch and Mux Devices
Patent:
6,614,291 →
Application:
09/881,950 →
High Speed Data Sampling with Reduced Metastability
Patent:
6,429,692 →
Application:
09/885,243 →
Coupling for Lc-Based Vco
Patent:
6,492,877 →
Application:
09/927,289 →
Buffering for Lc-Based Stage
Patent:
6,525,617 →
Application:
09/927,612 →
Enhanced Macrocell Module Having Expandable Product Term Sharing Capability for Use in High Density Cpld Architectures
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →
Release of Security Interest
May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →