Patent Assignment
Reel/Frame 012643/0710
Assignment of Assignor's Interest
Recorded: 2002-02-20
Received: 2002-03-11
Pages: 5
Assignor
AGERE SYSTEMS INC.
Executed: 2002-01-15
Assignee
LATTICE SEMICONDUCTOR CORPORATION
5555 NE MOORE COURT, HILLSBORO, OR, 97124, UNITED STATES
Covered Properties
(5)
Multi-Master Multi-Slave System Bus in a Field Programmable Gate Array (Fpga)
Application:
09/864,277 →
Signal Distribution Scheme in Field Programmable Gate Array (Fpga) or Field Programmable System Chip (Fpsc) Including Cycle Stealing Units
Application:
09/864,276 →
Double Data Rate Input and Output in a Programmable Logic Device
Application:
09/864,284 →
Multi-Functional I/O Buffers in a Field Programmable Gate Array (Fpga)
Application:
09/864,289 →
Field Programmable Gate Array (Fpga) Bit Stream Format
Application:
09/864,290 →