Patent Assignment
Reel/Frame 035220/0048
Security Interest
Recorded: 2015-03-17
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(100)
Continuous Time Programmable Analog Block Architecture
Patent:
5,574,678 →
Application:
08/396,994 →
Active Resistor for Stability Compensation
Patent:
5,617,064 →
Application:
08/403,352 →
Low Distortion Differential Transconductor Output Current Mirror
Patent:
5,493,205 →
Application:
08/403,354 →
Cmos Programmable Resistor-Based Transconductor
Patent:
5,510,738 →
Application:
08/403,359 →
Vbb Reference for Pumped Substrates
Patent:
5,670,907 →
Application:
08/403,595 →
Constant Delay Interconnect for Coupling Configurable Logic Blocks
Patent:
5,490,074 →
Application:
08/423,303 →
Cmos Memory Cell with Gate Oxide of Both Nmos and Pmos Transistors as Tunneling Window for Program and Erase
Patent:
5,596,524 →
Application:
08/427,117 →
Cascode Array Cell Partitioning for a Sense Amplifier of a Programmable Logic Device
Patent:
5,491,433 →
Application:
08/444,306 →
Completely Complementary Mos Memory Cell with Tunneling Through the Nmos and Pmos Transistors During Program and Erase
Patent:
5,594,687 →
Application:
08/447,991 →
Method of Making a Spacer Based Antifuse Structure for Low Capacitance and High Reliability
Patent:
5,756,367 →
Application:
08/449,384 →
Lead Frame with Noisy and Quiet V and V Leads Ss Dd
Patent:
5,570,046 →
Application:
08/453,184 →
Ground Bounce Isolated Output Buffer Polarity Control Circuit Which May Be Used W3ITH a Ground Bounce Limiting Buffer
Patent:
5,583,451 →
Application:
08/453,479 →
Programmable Logic Device with Internal Time-Constant Multiplexing of Signals from External Interconnect Buses
Patent:
5,621,650 →
Application:
08/456,946 →
Macrocell and Clock Signal Allocation Circuit for a Programmable Logic Device (Pld) Enabling Pld Resources to Provide Multiple Functions
Patent:
5,589,782 →
Application:
08/458,865 →
Multi-Tiered Hierarchical High Speed Switch Matrix Structure for Very High-Density Complex Programmable Logic Devices
Patent:
5,818,254 →
Application:
08/459,230 →
Programmable Uniform Symmetrical Distribution Logic Allocator for a High-Density Complex Pld
Patent:
5,781,030 →
Application:
08/459,234 →
Programmable Optimized-Distribution Logic Allocator for a High-Density Complex Pld
Patent:
6,531,890 →
Application:
08/459,570 →
P-Type Flip-Flop
Patent:
5,638,018 →
Application:
08/459,786 →
Very High-Density Complex Programmable Logic Devices with a Multi-Tiered Hierarchical Switch Matrix and Optimized Flixible Logic Allocation
Patent:
5,521,529 →
Application:
08/459,960 →
Array of Configurable Logic Blocks Including Cascadable Lookup Tables
Patent:
5,586,044 →
Application:
08/461,196 →
Array of Configurable Logic Blocks Each Including a First Lookup Table Output Coupled to Selectively Replace an Output of Second Lookup with an Alternate Function Output
Patent:
5,469,368 →
Application:
08/462,934 →
Low Power Cmos Array Cell for a Pld with Program and Erase Using Controlled Avalanche Injection
Patent:
5,754,471 →
Application:
08/466,438 →
System for Synthesizing Field Programmable Gate Array Implementations from High Level Circuit Descriptions
Patent:
5,594,657 →
Application:
08/473,620 →
An I/O Macrocell for a Programmable Logic Device
Patent:
5,612,631 →
Application:
08/474,629 →
Flexible Synchronous/Asynchronous Cell Structure for a High Density Programmable Logic Device
Patent:
5,811,986 →
Application:
08/474,635 →
A High Density Programmable Logic Device
Patent:
5,869,981 →
Application:
08/479,872 →
Multiple Array Programmable Logic Device with a Plurality of Programmable Switch Matrices
Patent:
5,617,042 →
Application:
08/483,623 →
A Flexible Block Clock Generation Circuit for Providing Clock Signals to Clocked Elements in a Multiple Array High Density Programmable Logic Divice
Patent:
5,594,365 →
Application:
08/486,174 →
Family of Multiple Segmented Programmable Logic Blocks Interconnected by a High Speed Centralized Switch Matrix
Patent:
5,764,078 →
Application:
08/486,178 →
Method and Apparatus for Converting Field-Programmable Gate Array Implementations into Mas-Programmable Logic Cell Implementations
Patent:
5,526,278 →
Application:
08/492,604 →
Isolation Using Self-Aligned Trench Formation and Conventional Locos
Patent:
5,679,599 →
Application:
08/493,640 →
Voltage Range Tolerant Cmos Output Buffer with Reduced Input Capacitance
Patent:
5,565,794 →
Application:
08/494,271 →
Non-Volatile Memory Cells Using Only Positive Charge to Store Data
Patent:
5,742,542 →
Application:
08/497,992 →
Method for Screening Non-Volatile Memory and Programmable Logic Devices
Patent:
5,700,698 →
Application:
08/500,295 →
Field Implant for Semiconductor Device
Patent:
5,604,370 →
Application:
08/501,230 →
Method for Simultaneous Programming of in-System Programmable Integrated Circuits
Patent:
5,635,855 →
Application:
08/505,837 →
Programmable Function Unit as Parallel Multiplier Cell
Patent:
5,570,039 →
Application:
08/507,893 →
Field Programmable Gate Array with Multi-Port Ram
Patent:
5,559,450 →
Application:
08/507,957 →
Interlaced Layout Configuration for Differential Pairs of Interconnect Lines
Patent:
5,581,126 →
Application:
08/528,030 →
Low-Skew Signal Routing in a Programmable Array
Patent:
5,528,170 →
Application:
08/535,362 →
Control Gate-Addressed Cmos Non-Volatile Cell That Programs Through Gates of Cmos Transistors
Patent:
5,615,150 →
Application:
08/551,974 →
Cmos Eeprom Cell with Tunneling Window in the Read Path
Patent:
5,587,945 →
Application:
08/554,092 →
Memory Cell for a Programmable Logic Device (Pld) Avoiding Pumping Programming Voltage Above an Nmos Threshold
Patent:
5,666,309 →
Application:
08/560,038 →
Array of Configurable Logic Blocks Each Including a Lookup Table Having Inputs Coupled Toa First Multiplexer and Having Outputs to a Second Multiplexer
Patent:
5,587,921 →
Application:
08/560,933 →
Method of Forming Multiple Gate Oxide Thicknesses on a Wafer Substrate
Patent:
5,672,521 →
Application:
08/561,306 →
Micropprocessor System with Process Identification Tag Entries to Reduce Cache Flushing After a Context Switch
Patent:
5,809,522 →
Application:
08/573,622 →
Deconvolution Input Buffer Compensating for Capacitance of a Switch Matrix of a High Density Programmable Logic Device
Patent:
5,739,713 →
Application:
08/574,776 →
Lock Generator Circuit for Use with a Dual Edge Register That Provides a Separate Enable for Each Edge of an Input Clock Signal
Patent:
5,719,516 →
Application:
08/575,852 →
Capacitance Elimination Circuit Which Provides Current to a Node in a Circuit to Eliminate the Effect of Parasitic Capacitance at the Node
Patent:
5,736,888 →
Application:
08/575,898 →
Array of Configurable Logic Blocks Including Network Means for Broadcasting Clock Signals to Different Pluralities of Logic Blocks
Patent:
5,598,346 →
Application:
08/596,679 →
Field Programmable Gate Array with Write-Port Enabled Memory
Patent:
5,623,217 →
Application:
08/606,702 →
Segment Descriptor Cache for a Processor
Patent:
5,926,841 →
Application:
08/614,728 →
Cmos Memory Cell with Tunneling During Program and Erase Through the Nmos and Pmos Transistors and a Pass Gate Separating the Nmos and Pmos Transistors
Patent:
5,646,901 →
Application:
08/625,403 →
Parallel Programming of in-System (Isp) Programmable Devices Using an Automatic Tester
Patent:
5,751,163 →
Application:
08/632,811 →
Active Resistor for Stability Compensation
Patent:
5,666,087 →
Application:
08/635,184 →
Method and Apparatus for in-System Programming of a Programmable Logic Device Using a Two-Wire Interface
Patent:
5,864,486 →
Application:
08/643,291 →
Array Cell Circuit with Split Read/Write Line
Patent:
5,748,525 →
Application:
08/643,807 →
A Method for Providing a Plurality of Hierarchical Signal Paths in a Very High-Density Programmable Logic Device
Patent:
5,789,939 →
Application:
08/653,186 →
Field Programmable Gate Array (Fpga) with Interconnect Encoding
Patent:
5,723,984 →
Application:
08/659,279 →
Field Programmable Gate Array (Fpga) Having an Improved Configuration Memory and Look Up Table
Patent:
5,808,942 →
Application:
08/659,941 →
Simplified Masking Process for Programmable Logic Device Manufacture
Patent:
5,830,795 →
Application:
08/664,190 →
A Clock Signal Providing Circuit with Enable and a Pulse Generator with Enable for Use in a Block Clock Circuit of a Programmable Logic Device
Patent:
5,760,609 →
Application:
08/666,193 →
Reference for Cmos Memory Cell Having Pmos and Nmos Transistors with a Common Floating Gate
Patent:
5,796,295 →
Application:
08/668,141 →
Programmable Logic Device with Multi-Level Power Control
Patent:
5,751,164 →
Application:
08/668,896 →
Temperature Insensitive Current Source
Patent:
5,818,294 →
Application:
08/683,373 →
Programmable Logic Device Having a Sense Amplifier with Virtual Ground
Patent:
5,734,275 →
Application:
08/683,685 →
An Integrated Circuit Having, and Process Providing, Different Oxide Layer Thicknesses on a Substrate
Patent:
5,942,780 →
Application:
08/689,523 →
Depletion Mode Pass Gates with Controlling Decoder and Negative Power Supply for a Programmable Logic Device
Patent:
5,801,551 →
Application:
08/690,768 →
Method for Programming a Programmable Logic Device in an Automatic Tester
Patent:
5,796,750 →
Application:
08/696,444 →
Oxide Formation Process for Manufacturing Programmable Logic Device
Patent:
5,960,274 →
Application:
08/699,401 →
Programmable Logic Device (Pld) Having Direct Connections Between Configurable Logic Blocks (Clbs) and Configurable Input/Output Blocks (Iobs)
Patent:
5,740,069 →
Application:
08/700,616 →
Decoder Circuit with Short Channel Depletion Transistors
Patent:
5,959,336 →
Application:
08/702,846 →
Configuration Pin Emulation Circuit for a Field Programmable Gate Array
Patent:
5,862,365 →
Application:
08/710,445 →
Programmable High Speed Routing Switch
Patent:
5,760,605 →
Application:
08/723,082 →
A Vpp Only Scalable Eeprom Memory Cell Having Transistors with Thin Tunnel Gate Oxide
Patent:
5,761,116 →
Application:
08/726,512 →
Method for Testing Field Programmable Gate Arrays
Patent:
5,991,907 →
Application:
08/729,117 →
Method for User-Controlled I/O Switching During in-Circuit Programming of Cplds Through the Ieee 1149.1 Test Access Port
Patent:
5,805,607 →
Application:
08/734,888 →
Block Clock and Initialization Circuit for a Complex High Density Pld
Patent:
5,811,987 →
Application:
08/740,948 →
Output Buffer Incorporating Shared Intermediate Nodes
Patent:
5,717,342 →
Application:
08/745,410 →
Fpga-Based Processor
Patent:
5,892,962 →
Application:
08/748,041 →
Timed Circuit Simulation in Hardware Using Fpga's
Patent:
6,028,993 →
Application:
08/781,882 →
Method of Charging and Discharging Floating Gate Transistors to Reduce Leakage Current
Patent:
5,841,701 →
Application:
08/785,096 →
Method and Apparatus Incorporating Nitrogen Selectively for Differential Oxide Growth
Patent:
5,904,575 →
Application:
08/799,153 →
Method to Incorporate, and a Device Having, Oxide Enhancement Dopants Using Gas Immersion Laser Doping (Gild) for Selectively Growing an Oxide Layer
Patent:
5,885,904 →
Application:
08/799,235 →
Process for Fabricating Semiconductor Memory Device with High Data Retention Including Silicon Nitride Etch Stop Layer Formed at High Temperature with Low Hydrogen Ion Concentration
Patent:
6,190,966 →
Application:
08/823,953 →
Application Specific Modules in a Programmable Logic Device
Patent:
5,835,405 →
Application:
08/827,671 →
Memory Bits Used to Couple Look Up Table Inputs to Facilitate Increased Availability to Routing Resources Particularly for Variable Sized Look Up Tables for a Field Programmable Gate Array (Fpga)
Patent:
5,905,385 →
Application:
08/828,520 →
Fast Verify for Cmos Memory Cells
Patent:
5,844,912 →
Application:
08/831,372 →
In-System Programmable Interconnect Circuit
Patent:
6,034,541 →
Application:
08/838,487 →
Reduction of N-Channel Parasitic Transistor Leakage by Using Low Power/Low Pressure Phosphosilicate Glass
Patent:
6,087,275 →
Application:
08/843,150 →
Devices for Sourcing Constant Supply Current from Power Supply in System with Integrated Circuit Having Variable Supply Current Requirement
Patent:
5,949,279 →
Application:
08/856,926 →
Process for Fabricating Semiconductor Memory Device with High Data Retention Including Silicon Oxynitride Etch Stop Layer Formed at High Temperature with Low Hydrogen Ion Concentration
Patent:
5,989,957 →
Application:
08/859,761 →
Nonvolatile Memory Structure for Programmable Logic Devices
Patent:
5,978,272 →
Application:
08/871,589 →
Fpga Having Predictable Open-Drain Drive Mode
Patent:
6,028,447 →
Application:
08/899,428 →
Output Buffer for Making a 5.0 Volt Compatible Input/Output in a 2.5 Volt Semiconductor Process
Patent:
6,072,351 →
Application:
08/912,763 →
Circuitry to Provide Fast Carry
Patent:
6,359,466 →
Application:
08/931,798 →
Hybrid Programmable Gate Arrays
Patent:
6,020,755 →
Application:
08/938,550 →
Data Retention of Eeprom Cell with Shallow Trench Isolation Using Thicker Liner Oxide
Patent:
5,854,114 →
Application:
08/947,888 →
Variable Grain Architecture for Fpga Integrated Circuits
Patent:
6,097,212 →
Application:
08/948,306 →
Programmable Clock Manager for a Programmable Logic Device That Can Generate at Least Two Different Output Clocks
Patent:
6,028,463 →
Application:
08/949,992 →
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.