IP Library › Granted Patent US 6,130,551
Granted Patent Utility
US 6,130,551 · App. 09/008,762

Synthesis-friendly FPGA architecture with variable length and variable timing interconnect

Inventors: Om P. Agrawal, Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen
Patented Case View Patent ↗
Granted: Oct 10, 2000 Filed: Jan 19, 1998
Inventors
Om P. Agrawal
Herman M. Chang
Bradley A. Sharpe-Geisler
Giap H. Tran
Bai Nguyen
Assignee (at issue)
Vantis Corporation

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Quick Facts
Patent No.
US 6,130,551
App. No.
09/008,762
Filed
1998-01-19
Granted
2000-10-10
Kind
A