Granted Patent
Utility
US 6,130,551 · App. 09/008,762
Synthesis-friendly FPGA architecture with variable length and variable timing interconnect
Inventors:
Om P. Agrawal, Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen
Patented Case
View Patent ↗
Granted: Oct 10, 2000
Filed: Jan 19, 1998
Inventors
Om P. Agrawal
Herman M. Chang
Bradley A. Sharpe-Geisler
Giap H. Tran
Bai Nguyen
Assignee (at issue)
Vantis Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.