HD physical layer of a wireless communication device
View Patent ↗A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).
1. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the HRP comprises an outer code circuit, an outer interleaver circuit, M inner encoders, where M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of an outer code codeword to a different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code; and
wherein the LRP is operable to generate a LRP data packet for acknowledgement of HRP packets.
2. The apparatus of claim 1 wherein the high rate physical layer circuit (HRP) is to produce data rates in the order of gigabits per second, and the low rate physical layer circuit (LRP) is to produce data rates in the order of megabits per second.
3. The apparatus of claim 1 wherein three low rate channels generated by the low rate physical layer circuit (LRP) are allocated within one high rate channel generated by the high rate physical layer circuit (HRP).
4. The apparatus of claim 1 wherein the low rate channels and the high rate channels operate in time-division duplex (TDD).
5. The apparatus of claim 1 wherein the radio frequency (RF) transmitter comprises one crystal to generate immediate frequency (IF) and RF.
6. The apparatus of claim 1 wherein the high rate physical layer circuit (HRP) is to produce one or more wireless signal occupying about 1.7 GHz bandwidth.
7. The apparatus of claim 1 wherein the high rate physical layer circuit (HRP) is to produce a directional beam-formed signal for the RF transmitter.
8. The apparatus of claim 1 wherein the high rate physical layer circuit (HRP) is associated with the transmission of audio, video, data, and control messages.
9. The apparatus of claim 1 wherein the low rate physical layer circuit (LRP) further is to produce one or more wireless signals occupying a sub-channel of about 91 MHz bandwidth.
10. The apparatus of claim 1 wherein the low rate physical layer circuit (LRP) further is to produce a directional signal, an omni-directional signal, or a beam-formed signal for the RF transmitter.
11. The apparatus of claim 1 wherein the low rate physical layer circuit (LRP) is associated with control messages, beacons, acknowledgements, and low-speed data.
12. The apparatus of claim 1 wherein the HRP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, a bit interleaver circuit, a tone interleaver circuit, and a data scrambler circuit.
13. The apparatus of claim 1 wherein the LRP comprises a pilot tone circuit, a tone interleaver circuit, a Forward Error Correction (FEC) circuit, and a data scrambler circuit.
14. The apparatus of claim 1 wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet.
15. The apparatus of claim 14 wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload.
16. The apparatus of claim 15 wherein the LRP header is coded by a tail biting convolutional code.
17. The apparatus of claim 15 wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble.
18. The apparatus of claim 17 wherein the long Omni LRP preamble is about 57 μsec long.
19. The apparatus of claim 14 wherein the LRP short directional data packet is configured for acknowledgement of HRP packets and beam-formed LRP packets.
20. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP), wherein the radio frequency (RF) transmitter comprises one crystal to generate immediate frequency (IF) and F, wherein the crystal generates four channels centers between about 57 GHz and about 66 GHz;
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).
21. The apparatus of claim 20 wherein the four channels comprises 58.608 GHz, 60.720 GHz, 62.832 GHz, and 64.944 GHz.
22. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the HRP comprise an outer code circuit, an outer interleaver circuit, and M inner code circuits,
wherein M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of the outer code codeword to different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code.
23. The apparatus of claim 22 wherein the outer interleaver circuit is to further divide the input bytes into a group of consecutive M bytes, input the M bytes to consecutive bytes of the outer code, and map the M bytes to M different inner code.
24. The apparatus of claim 22 further comprising:
a bit interleaver circuit that maps bits from a same inner code to an equal number of Most Significant Bits (MSB and Least Significant Bits (LSBs) of the signal constellation.
25. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the long Omni LRP preamble is configured for beacons and for LRP data packets with blind timing synchronization.
26. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the long Omni LRP preamble comprises a first automatic gain control (AGC) and signal detection segment, a coarse frequency offset estimation (FOE) and timing recovery segment, a fine FOE and timing recovery segment, and a receiver beam-forming segment, a second AGC segment, and a channel estimation segment.
27. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble is about 43 μsec long.
28. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble is configured for contention period and for LRP data packets with timing synchronization.
29. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble comprises a first automatic gain control (AGC) segment, a second AGC segment, a signal detection and time synch segment, a receiver beam-forming segment, a third AGC segment, and a channel estimation segment.
30. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet, an LRP Beam-formed data packet, and a LRP Short Directional data packet, wherein the LRP Beam-formed data packet comprises a LRP Beam-formed preamble, a LRP Beam-formed header, and a LRP Beam-formed payload.
31. The apparatus of claim 30 wherein the LRP Beam-formed preamble comprises a frame synch and automatic gain control (AGC) segment, and a channel estimation segment.
32. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; and
a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP short directional data packet comprises a LRP short directional preamble, and a LRP short directional header.
33. The apparatus of claim 32 wherein the LRP short directional data packet further comprises a LRP short directional payload.
34. The apparatus of claim 32 wherein the LRP short directional preamble comprises an automatic gain control (AGC) segment, and a channel estimation segment.
35. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to and controlled by the processor to transmit data or content;
an interface to a wireless communication channel coupled to the processor to communicate antenna information relating to the use of the phased array antenna and to communicate information to facilitate receiving the data or playing the content at another location; and
a physical layer circuit coupled to the RF transmitter and the interface for encoding and decoding between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP); and
wherein the HRP comprises an outer code circuit, an outer interleaver circuit, M inner code circuits, where M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of an outer code codeword to a different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code.
36. The apparatus of claim 35 wherein the high rate physical layer circuit (HRP) is operable to produce data rates in the order of gigabits per second, and the low rate physical layer circuit (LRP) is to produce data rates in the order of megabits per second.
37. The apparatus of claim 35 wherein three low rate channels generated by the low rate physical layer circuit (LRP) are allocated within one high rate channel generated by the high rate physical layer circuit (HRP).
38. The apparatus of claim 35 wherein:
the high rate physical layer circuit (HRP) is to produce one or more wireless signal occupying about 1.7 GHz bandwidth;
the high rate physical layer circuit (HRP) is to produce data rates in the order of gigabits per second; and
the low rate physical layer circuit (LRP) is to produce data rates in the order of megabits per second.
39. The apparatus of claim 35 wherein the high rate physical layer circuit (HRP) is to produce a directional beam-formed signal for the RF transmitter.
40. The apparatus of claim 35 wherein the high rate physical layer circuit (HRP) is associated with the transmission of audio, video, data, and control messages.
41. The apparatus of claim 35 wherein the low rate physical layer circuit (LRP) is to produce one or more wireless signals occupying a sub-channel of about 91 MHz bandwidth.
42. The apparatus of claim 35 wherein the low rate physical layer circuit (LRP) is to produce a directional signal, an omni-directional signal, or a beam-formed signal for the RF transmitter.
43. The apparatus of claim 35 wherein the low rate physical layer circuit (LRP) is associated with control messages, beacons, acknowledgements, and low-speed data.
44. The apparatus of claim 35 wherein the HRP comprises an outer code circuit, an outer interleaver circuit, an inner code circuit, a bit interleaver circuit, a tone interleaver circuit, and a data scrambler circuit.
45. The apparatus of claim 35 wherein the outer interleaver circuit is to further divide the input bytes into a group of consecutive M bytes, input the M bytes to consecutive bytes of the outer code, and map the M bytes to M different inner code.
46. The apparatus of claim 45 further comprising:
a bit interleaver circuit that maps bits from a same inner code to an equal number of Most Significant Bits (MSB) and Least Significant Bits (LSB) of the signal constellation.
47. The apparatus of claim 35 wherein the LRP comprises a pilot tone circuit, a tone interleaver circuit, a Forward Error Correction (FEC) circuit, and a data scrambler circuit.
48. The apparatus of claim 35 wherein the LRP is configured to generate a LRP Long Omni data packet, a LRP Beam-formed data packet, and a LRP Short Directional data packet.
49. The apparatus of claim 48 wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload.
50. The apparatus of claim 49 wherein the LRP header is coded by a tail biting convolutional code.
51. The apparatus of claim 49 wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble.
52. The apparatus of claim 51 wherein the long Omni LRP preamble is about 57 μsec long.
53. The apparatus of claim 51 wherein the long Omni LRP preamble is configured for beacons and for LRP data packets with blind timing synchronization.
54. The apparatus of claim 51 wherein the long Omni LRP preamble comprises a first automatic gain control (AGC) and signal detection segment, a coarse frequency offset estimation (FOE) and timing recovery segment, a fine FOE and timing recovery segment, and a receiver beam-forming segment, a second AGC segment, and a channel estimation segment.
55. The apparatus of claim 51 wherein the short Omni LRP preamble is about 43 μsec long.
56. The apparatus of claim 51 wherein the short Omni LRP preamble is configured for contention period and for LRP data packets with timing synchronization.
57. The apparatus of claim 51 wherein the short Omni LRP preamble comprises a first automatic gain control (AGC) segment, a second AGC segment, a signal detection and time synch segment, a receiver beam-forming segment, a third AGC segment, and a channel estimation segment.
58. The apparatus of claim 48 wherein the LRP Beam-formed data packet comprises a LRP Beam-formed preamble, a LRP Beam-formed header, and a LRP Beam-formed payload.
59. The apparatus of claim 58 wherein the LRP Beam-formed preamble comprises a frame synch and automatic gain control (AGC) segment, and a channel estimation segment.
60. The apparatus of claim 58 wherein the LRP short directional data packet comprises a LRP short directional preamble, and a LRP short directional header.
61. The apparatus of claim 60 wherein the LRP short directional preamble comprises an automatic gain control (AGC) segment, and a channel estimation segment.
62. The apparatus of claim 58 wherein the LRP short directional data packet comprises a LRP short directional preamble, a LRP short directional header, and a LRP short directional payload.
63. The apparatus of claim 58 wherein the LRP short directional data packet is configured for acknowledgement of HRP packets and beam-formed LRP packets.
64. An apparatus comprising:
a processor;
a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit content;
a physical layer circuit coupled to the RF transmitter and the processor for encoding and decoding between a digital signal and a modulated analog signal,
wherein the physical layer circuit comprises a low rate physical layer circuit (LRP) capable of operating in a directional mode or an omni-directional mode for the RF transmitter,
wherein in the omni-directional mode, the physical layer circuit is to generate a same signal replicated N times, each replication using a different TX antenna phase pattern, and wherein in the directional mode, the physical layer circuit is to generate a same signal replicated N+1 times, each replication uses a same optimal TX antenna phase pattern, the optimal TX antenna phase pattern feedback to a back channel transmitter from a back channel receiver.
65. The apparatus of claim 64 wherein the signal includes an orthogonal frequency division multiplex (OFDM) symbol, and N=8.
66. The apparatus of claim 64 wherein the signal includes an orthogonal frequency division multiplex (OFDM) symbol, and N=8.
67. The apparatus of claim 64 wherein the LRP is configured to generate a LRP Long Omni data packet, a LRP Beam-formed data packet, and a LRP Short Directional data packet.
68. The apparatus of claim 67 wherein the LRP short directional data packet is configured for acknowledgement of HRP packets and beam-formed LRP packets.