Power sequence controller programming technique

1. A method of programming a programmable logic device (PLD), wherein the PLD controls a circuit's behavior according to a desired circuit behavior implementation, comprising:

(a) reading a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching that implement the desired circuit behavior;

(b) translating the program into an abstract state sequencer;

(c) translating the abstract state sequencer into hardware description language (HDL) source code as governed by the programmable architecture of the PLD; and

(d) translating the HDL source code into a programming bit pattern used to program the PLD.

2. The method of claim 1 , wherein the PLD comprises a power sequence controller and wherein the program in act (a) comprises a power supply program that describes the desired power sequence behavior.

3. The method of claim 2 , wherein the abstract state sequencer of act (b) is a one-clock-cycle-per-instruction state sequencer and includes an individual state for each power supply program instruction.

4. The method of claim 2 , wherein the abstract state sequencer of act (b) is a multiple-clock-cycle-per-instruction state sequencer and includes an individual state for each clock cycle per power supply program instruction.

5. The method of claim 2 , wherein the HDL source code formed in act (c) is ABEL source code.

6. The method of claim 2 , wherein the HDL source code formed in act (c) is VHDL source code.

7. The method of claim 2 , further comprising:

identifying states created in act (b) that will be subject to an exception, wherein the exception defines a Boolean expression such that if the Boolean expression is satisfied, the abstract state sequencer will synchronously go to a specified state.

8. The method of claim 7 , wherein the exception also defines a Boolean expression such that if the Boolean expression is satisfied, the abstract state sequencer is asynchronously reset.

9. The method of claim 1 , further comprising:

programming the PLD with the programming bit pattern.

10. A computer readable medium on which is stored a computer program for executing the method of claim 1 .

11. A method of programming a programmable power sequence controller, comprising:

reading a power supply program, wherein the program comprises instructions defining desired controller behavior in terms of inputs, outputs, and conditional branching;

translating the instructions of the power supply program into hardware description language (HDL) code; and

translating the HDL code into a programming bit pattern used to program the power sequence controller.

12. The method of claim 11 , wherein an abstract state machine defined by the power supply program instructions includes one or more clock cycles per instruction.

13. The method of claim 11 , wherein the power supply program instructions include instructions from an instruction set that includes one or more of the following member instruction formats:

WaitFor a <Boolean expression>;

Turn on <output signal>;

Turn off <output signal>;

Assert (output signal);

Release (output signal);

If (<Boolean expression> THEN <ThenStep> Else <ElseStep>;

Wait for (timeout value) using Timer <number>;

GoTo <Gotostep>;

Halt; or

Nop.

14. The method of claim 13 , wherein the instruction set includes all of the member instruction formats.

15. The method of claim 11 , wherein the HDL source code is ABEL source code.

16. The method of claim 11 , wherein the HDL source code is VHDL source code.

17. The method of claim 11 , wherein the act of translating the instructions of the power supply program into hardware description language (HDL) code comprises:

translating the program instructions into an intermediate set of instructions that takes into account the number of clock cycles of the program instruction being translated; and

translating the intermediate set of instructions into HDL code.

18. The method of claim 11 , including programming the programmable power sequence controller with the programming bit pattern.

19. A computer readable medium on which is stored a computer program for executing the following instructions for programming a programmable power sequence controller:

reading a power supply program, wherein the program comprises instructions defining desired controller behavior in terms of inputs, outputs, and conditional branching;

translating the instructions of the power supply program into hardware description language (HDL) code; and

translating the HDL code into a programming bit pattern used to program the power sequence controller.

20. The computer readable medium of claim 19 , wherein the computer program includes instructions for programming the programmable power sequence controller with the programming bit pattern.