Patent Assignment
Reel/Frame 035308/0428
Security Interest
Recorded: 2015-03-24
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(100)
Low Voltage Bandgap Reference Circuit
Patent:
6,489,835 →
Application:
09/941,454 →
Method to Improve the Reliability of Thermosonic Gold to Aluminum Wire Bonds
Multiple Width Random Number Generation
Patent:
6,832,231 →
Application:
09/966,967 →
Zero-Power Programmable Memory Cell
Patent:
6,611,463 →
Application:
09/991,245 →
Zero-Power Logic Cell for Use in Programmable Logic Devices
Patent:
6,489,806 →
Application:
09/992,493 →
Digital Phase Locked Loop with Programmable Digital Filter
Patent:
6,993,108 →
Application:
10/006,516 →
Digital Phase Locked Loop with Phase Selector Having Minimized Number of Phase Interpolators
Patent:
7,003,066 →
Application:
10/006,559 →
Clock Data Recovery Deserializer with Programmable Sync Detect Logic
Patent:
6,999,543 →
Application:
10/006,610 →
Non-Volatile Memory Cell with Enhanced Cell Drive Current
Patent:
6,515,899 →
Application:
10/010,011 →
Single-Poly Two-Transistor Eeprom Cell with Differentially Doped Floating Gate
Patent:
6,693,830 →
Application:
10/011,549 →
Data Storage Systems with Enhanced Cooling
Patent:
6,636,422 →
Application:
10/014,905 →
Programmable Input/Output Cell with Bidirectional and Shift Register Capabilities
Patent:
6,674,303 →
Application:
10/017,725 →
Structure and Method for Implementing Wide Multiplexers
Patent:
6,605,959 →
Application:
10/017,859 →
I/O Block for a Programmable Interconnect Circuit
Patent:
6,703,860 →
Application:
10/021,844 →
Programmable Interconnect Circuit with a Phase-Locked Loop
Patent:
6,661,254 →
Application:
10/021,873 →
Block-Oriented Architecture for a Programmable Interconnect Circuit
Patent:
7,154,298 →
Application:
10/022,464 →
Multi-Level Routing Structure for a Programmable Interconnect Circuit
Patent:
6,653,861 →
Application:
10/023,053 →
High Speed Interface for a Programmable Interconnect Circuit
Test structure for determining a minimum tunnel opening size in a non-volatile memory
Method of Preventing High Icc at Start-Up in Zero-Power Eeprom Cells for Pld Applications
Symmetrical Cml Logic Gate System
Patent:
6,680,625 →
Application:
10/066,031 →
Integrated Circuit Base Transistor Structure and Associated Programmable Cell Library
Eeprom with a Neutralized Doping at Tunnel Window Edge
Patent:
6,600,188 →
Application:
10/083,728 →
Variable Grain Architecture for Fpga Integrated Circuits
Integrated Delay Discriminator for Use with a Field-Programmable Gate Array and a Method of Determining a Time Delay Thereof
Patent:
6,795,959 →
Application:
10/103,100 →
Fft Address Generation Method and Apparatus
Patent:
6,907,439 →
Application:
10/106,509 →
Skipped Carry Incrementer for Fft Address Generation
Patent:
6,976,047 →
Application:
10/108,401 →
Differential Input Comparator
Patent:
6,639,431 →
Application:
10/112,370 →
Zero Power Memory Cell with Improved Data Retention
Patent:
6,660,579 →
Application:
10/128,943 →
Polynomial Expander for Generating Coefficients of a Polynomial from Roots of the Polynomial
Patent:
7,032,162 →
Application:
10/131,883 →
Device and Method with Generic Logic Blocks
Integrated Circuit and Associated Design Method with Antenna Error Control Using Spare Gates
Integrated Circuit and Associated Design Method Using Spare Gate Islands
Band Gap Reference Circuit
Patent:
6,720,755 →
Application:
10/146,734 →
Input Buffer with Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,714,048 →
Application:
10/146,739 →
Input Buffer with Cmos Driver Gate Current Control Enabling Selectable Pcl, Gtl, or Pecl Compatibility
Patent:
6,870,391 →
Application:
10/146,769 →
Output Buffer with Feedback from an Input Buffer to Provide Selectable Pcl, Gtl or Pecl Compatibility
Patent:
6,657,458 →
Application:
10/146,826 →
Electrostatic Discharge Protection Circuit
Patent:
6,760,209 →
Application:
10/147,011 →
Output Buffer Having Programmable Drive Current and Output Voltage Limits
Patent:
6,714,043 →
Application:
10/147,199 →
Method of Assigning Logic Functions to Macrocells in a Programmable Logic Device
Patent:
6,848,095 →
Application:
10/150,410 →
Output Buffer with Overvoltage Protection
Patent:
6,798,244 →
Application:
10/151,753 →
Highly Linear Programmable Transconductor with Large Input-Signal Range
Patent:
6,583,652 →
Application:
10/159,009 →
Precision Analog Level Shifter with Programmable Options
Patent:
6,717,451 →
Application:
10/159,089 →
Multimode Output Stage Converting Differential to Single-Ended Signals Using Current-Mode Input Signals
Patent:
6,806,771 →
Application:
10/159,681 →
Eeprom Device with Improved Capacitive Coupling and Fabrication Process
Patent:
6,794,236 →
Application:
10/160,855 →
Eeprom Device Having a Retrograde Program Junction Region and Process for Fabricating the Device
Patent:
6,716,705 →
Application:
10/161,283 →
Shallow Junction Eeprom Device and Process for Fabricating the Device
Patent:
6,596,587 →
Application:
10/162,337 →
Semiconductor Device Having Metallized Interconnect Structure and Method of Fabrication
Patent:
6,703,305 →
Application:
10/164,484 →
Converting Bits to Vectors in a Programmable Logic Device
Field Programmable Gate Array Based Upon Transistor Gate Oxide Breakdown
Patent:
6,650,143 →
Application:
10/191,888 →
Fpga with Register-Intensive Architecture
Patent:
7,028,281 →
Application:
10/194,771 →
Integrated Programmable Continuous Time Filter with Programmable Capacitor Arrays
Memory Cell
Patent:
6,683,477 →
Application:
10/207,292 →
Crc Calculation System and Method for a Packet Arriving on an N-Byte Wide Bus
Eeprom Tunnel Window for Program Injection via P+ Contacted Inversion
Patent:
6,545,313 →
Application:
10/211,125 →
Enhanced Cpld Macrocell Module Having Selectable Bypass of Steering-Based Resource Allocation and Methods of Use
Patent:
6,650,142 →
Application:
10/219,046 →
Eeprom Device Having an Isolation-Bounded Tunnel Capacitor and Fabrication Process
Patent:
6,841,447 →
Application:
10/232,912 →
Performing Conditional Operations in a Programmable Logic Device
Patent:
7,043,511 →
Application:
10/233,021 →
Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in Fpga Device
Patent:
6,725,442 →
Application:
10/235,380 →
Device Having Electically Isolated Low Voltage and High Voltage Regions and Process for Fabricating the Device
Patent:
6,833,602 →
Application:
10/236,114 →
Eeprom Device Having Improved Data Retention and Process for Fabricating the Device
Patent:
6,649,514 →
Application:
10/236,718 →
Eeprom Cell Having a Floating-Gate Transistor Within a Cell Well and a Process for Fabricating the Memory Cell
Patent:
6,842,372 →
Application:
10/236,829 →
Sram Cell with Single-Ended and Differential Read/Write Ports
Memory Access Circuit and Method for Reading and Writing Data with the Same Clock Signal
Patent:
6,917,536 →
Application:
10/243,014 →
Eeprom Cell with Trench Coupling Capacitor
Patent:
6,700,154 →
Application:
10/251,608 →
Method of Routing in a Programmable Logic Device
Patent:
6,907,592 →
Application:
10/255,474 →
State Machine in a Programmable Logic Device
Patent:
6,803,787 →
Application:
10/255,499 →
Vector Routing in a Programmable Logic Device
Patent:
6,812,738 →
Application:
10/255,656 →
Method of Optimizing Routing in a Programmable Logic Device
Patent:
6,809,551 →
Application:
10/255,875 →
Programming Programmable Logic Devices Using Hidden Switches
Patent:
6,748,575 →
Application:
10/263,251 →
Voltage Limited Eeprom Device and Process for Fabricating the Device
Patent:
6,846,714 →
Application:
10/263,507 →
Low Voltage Differential Signaling Systems and Methods
Patent:
6,639,434 →
Application:
10/266,361 →
Verify Scheme for a Multi-Level Routing Structure
Patent:
6,762,618 →
Application:
10/269,439 →
Power Supply Control Circuits
Expansion Method for Complex Power-Sequencing Applications
Patent:
7,111,183 →
Application:
10/269,804 →
Power Sequence Controller Programming Technique
Patent:
6,901,572 →
Application:
10/272,582 →
Asynchronous Glitch-Free Clock Multiplexer
Patent:
6,639,449 →
Application:
10/278,415 →
Turbo Encoder with Reduced Processing Delay
Patent:
7,051,261 →
Application:
10/282,524 →
Programmable Common Mode Termination for Input/Output Circuits
Patent:
6,700,823 →
Application:
10/283,765 →
Adaptive Adjustment of Constraints During Pld Placement Processing
Placement Processing for Programmable Logic Devices
Low Jitter Integrated Phase Locked Loop with Broad Tuning Range
Patent:
6,825,733 →
Application:
10/300,190 →
Flash Technology Transistors and Methods for Forming the Same
Patent:
6,797,568 →
Application:
10/302,439 →
Bandgap Reference Circuit for Improved Start-Up
Patent:
6,710,641 →
Application:
10/308,420 →
Coupling for Lc-Based Vco
Patent:
6,650,188 →
Application:
10/309,302 →
Fifo Memory Architecture
Patent:
6,777,979 →
Application:
10/334,642 →
Programmable Optimized-Distribution Logic Allocator for a High-Density Complex Pld
Patent:
6,753,696 →
Application:
10/338,619 →
Adaptive Input Logic for Phase Adjustments
Programmable Interface Circuit for Differential and Single-Ended Signals
Noise Reduction Techniques for Programmable Input/Output Circuits
Patent:
6,812,869 →
Application:
10/367,323 →
Macrocells Supporting a Carry Cascade
Patent:
6,915,323 →
Application:
10/368,023 →
Dynamic Cross Point Switch with Shadow Memory Architecture
Patent:
6,861,870 →
Application:
10/370,232 →
Bank-Based Input/Output Buffers with Multiple Reference Voltages
Patent:
6,859,066 →
Application:
10/377,320 →
Pointer Processing for Optical Communication Systems
Patent:
7,339,952 →
Application:
10/387,243 →
Automatic Lane Assignment for a Receiver
Patent:
7,305,047 →
Application:
10/387,814 →
Programmable Logic Devices with Integrated Standard-Cell Logic Blocks
Fpga Integrated Circuit Having Embedded Sram Memory Blocks with Registered Address and Data Input Sections
Patent:
39,510 →
Application:
10/392,751 →
Electronic Circuit with on-Chip Programmable Terminations
Patent:
6,967,500 →
Application:
10/397,669 →
Method and Apparatus for Controlling Signal Distribution in an Electronic Circuit
Patent:
6,873,187 →
Application:
10/400,705 →
Hierarchical General Interconnect Architecture for High Density Fpga's
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →