Granted Patent
Utility
US 6,154,051 · App. 09/187,689
Tileable and compact layout for super variable grain blocks within FPGA device
Inventors:
Bai Nguyen, Om P. Agrawal, Bradley A. Sharpe-Geisler, Jack T. Wong, Herman M. Chang, Giap H. Tran
Patented Case
View Patent ↗
Granted: Nov 28, 2000
Filed: Nov 5, 1998
Inventors
Bai Nguyen
Om P. Agrawal
Bradley A. Sharpe-Geisler
Jack T. Wong
Herman M. Chang
Giap H. Tran
Assignee (at issue)
Vantis Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.