Early global set/reset signal determination for programmable logic devices

1. A method comprising:

receiving a user design for a programmable logic device (PLD), wherein the PLD comprises a plurality of configurable resources, global set/reset (GSR) resources, and a plurality of sequential components;

identifying a plurality of set/reset signals of the user design;

determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources; and

assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement, wherein

the user design identifies connections between the set/reset signals and the sequential components; and the determining a measurement comprises filtering the sequential components, and determining configurable resource savings associated with assigning the set/reset signal to the GSR resources connected to the filtered sequential components.

2. The method of claim 1 , wherein the sequential component is a flip-flop.

3. A method of claim 1 , comprising:

receiving a user design for a programmable logic device (PLD), wherein the PLD comprises a plurality of configurable resources, global set/reset (GSR) resources;

identifying a plurality of set/reset signals of the user design;

determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources; and

assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement,

wherein the user design identifies a non-sequential logic component implementable by the configurable resources of the PLD and further identifies a connection between the selected set/reset signal and the logic component, the assigning comprises reassigning the selected set/reset signal from the logic component to the GSR resources and the method further comprises removing the logic component from the user design.

4. The method of claim 1 , wherein:

the user design comprises a plurality of partitions; and

the identifying and determining are performed independently for each partition of the user design.

5. The method of claim 1 , wherein the filtering comprises identifying the sequential components receiving at least two of the set/reset signals.

6. The method of claim 5 , wherein the at least two set/reset signals comprise one synchronous set/reset signal and one asynchronous set/reset signal.

7. The method of claim 5 , wherein the at least two set/reset signals are both set signals or both reset signals.

8. The method of claim 1 , wherein:

the identifying, determining, and assigning are performed as part of a synthesis process to convert the user design to a synthesized design; and

the method further comprises: mapping the synthesized design to a plurality of PLD component types, and assigning the mapped PLD component types to physical components of the PLD.

9. A system comprising:

a processor; and

a memory configured to store a plurality of computer readable instructions which when executed by the processor are configured to cause the system to perform a method comprising:

receiving a user design for a programmable logic device (PLD), wherein the PLD comprises a plurality of configurable resources, global set/reset (GSR) resources and a plurality of sequential components,

identifying a plurality of set/reset signals of the user design,

determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources, and

assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement, wherein the user design identifies connections between the set/reset signals and the sequential components; and the determining a measurement comprises filtering the sequential components, and determining configurable resource savings associated with assigning the set/reset signal to the GSR resources connected to the filtered sequential components.

10. The system of claim 9 , wherein:

the PLD further comprises a sequential component connected to the GSR resources;

the user design identifies a connection between the selected set/reset signal and a data input port of the sequential component; and

the assigning comprises reassigning the selected set/reset signal from the data input port to the GSR resources.

11. The system of claim 10 , wherein the sequential component is a flip-flop.

12. The system of claim 9 , wherein:

the user design identifies a non-sequential logic component implementable by the configurable resources of the PLD and further identifies a connection between the selected set/reset signal and the logic component;

the assigning comprises reassigning the selected set/reset signal from the logic component to the GSR resources; and

the method further comprises removing the logic component from the user design.

13. The system of claim 9 , wherein:

the user design comprises a plurality of partitions; and the identifying and determining are performed independently for each partition of the user design.

14. The system of claim 1 , wherein the filtering comprises identifying the sequential components receiving at least two of the set/reset signals.

15. The system of claim 14 , wherein the at least two set/reset signals comprise one synchronous set/reset signal and one asynchronous set/reset signal.

16. The system of claim 14 , wherein the at least two set/reset signals are both set signals or both reset signals.

17. The system of claim 9 , wherein the identifying, determining, and assigning are performed as part of a synthesis process to convert the user design to a synthesized design, and

the method further comprises:

mapping the synthesized design to a plurality of PLD component types, and

assigning the mapped PLD component types to physical components of the PLD.