Patent Assignment
Reel/Frame 035225/0352
Security Interest
Recorded: 2015-03-19
Pages: 83
Assignors
LATTICE SEMICONDUCTOR CORPORATION
Executed: 2015-03-10
SIBEAM, INC.
Executed: 2015-03-10
SILICON IMAGE, INC.
Executed: 2015-03-10
DVDO, INC.
Executed: 2015-03-10
Assignee
JEFFERIES FINANCE LLC
520 MADISON AVENUE, NEW YORK, NEW YORK, 10022
Covered Properties
(100)
Field Programmable Gate Array Having a Dedicated Processor Interface
Patent:
6,216,191 →
Application:
08/950,444 →
Bi-Directional Buffers and Supplemental Logic and Interconnect Cells for Programmable Logic Devices
Patent:
5,986,471 →
Application:
08/950,446 →
Programmable Clock Manager for a Programmable Logic Device That Can Be Programmed Without Reconfiguring the Device
Patent:
6,060,902 →
Application:
08/950,448 →
Programmable Logic Device with Logic Cells Having a Flexible Input Structure
Patent:
6,049,224 →
Application:
08/950,624 →
Programmable Clock Manager for a Programmable Logic Device That Can Implement Delay-Locked Loop Functions
Patent:
6,043,677 →
Application:
08/951,128 →
Simultaneous Wired and Wireless Remote in-System Programming of Multiple Remote Systems
Method for Testing Field Programmable Gate Arrays
Patent:
6,003,150 →
Application:
08/974,799 →
Flexible Direct Connections Between Input/Output Blocks (Iobs) and Variable Grain Blocks (Vgbs) in Fpga Integrated Circuits
Patent:
5,990,702 →
Application:
08/995,612 →
Input/Output Block (Iob) Connections to Maxl Lines nor Lines and Dendrites in Fpga Integrated Circuits
Patent:
5,982,193 →
Application:
08/995,614 →
Programmable Input/Output Block (Iob) in Fpga Integrated Circuits
Patent:
6,034,544 →
Application:
08/995,615 →
Dual Port Sram Memory for Run Time Use in Fpga Integrated Circuits
Patent:
6,127,843 →
Application:
08/996,049 →
Multiple Input Zero Power and /nor Gate for Use in a Field Programmable Gate Array (Fpga)
Patent:
5,986,480 →
Application:
08/996,119 →
Symmetical, Extended and Fast Direct Connections Between Variable Grain Blocks in Fpga Integrated Circuits
Patent:
6,275,064 →
Application:
08/996,361 →
Process for Programming Plds and Embedded Non-Volatile Memories
Patent:
6,134,703 →
Application:
08/996,530 →
Programmable Control Multiplexing for Input/Output Blocks (Iobs) in Fpga Integrated Circuits
Patent:
6,107,823 →
Application:
08/997,221 →
Electrically Erasable and Reprogrammable, Nonvolatile Integrated Storage Device with in-System Programming and Verification (Ispav) Capabilities for Supporting in-System Reconfiguring of Pld's
Patent:
6,102,963 →
Application:
08/998,978 →
Synthesis-Friendly Fpga Architecture with Variable Length and Variable Timing Interconnect
Patent:
6,130,551 →
Application:
09/008,762 →
Virtual Logic System for Reconfigurable Hardware
Patent:
6,034,538 →
Application:
09/010,000 →
Sequential and Simultaneous Manufacturing Programming of Multiple in-System Programmable Systems Through a Data Network
Patent:
6,023,570 →
Application:
09/023,506 →
Spacer-Based Antifuse Structure for Low Capacitance and High Reliability and Method of Fabrication Thereof
Patent:
6,025,637 →
Application:
09/023,669 →
Eeprom Cell with Field-Edgeless Tunnel Window Using Shallow Trench Isolation Process
Patent:
6,093,946 →
Application:
09/026,814 →
Programmable Gate Array with Improved Interconnect Structure, Input/Output Structure and Configuable Logic Block
Patent:
6,128,770 →
Application:
09/037,095 →
Global Signal Distribution with Reduced Routing Tracks in an Fpga
Patent:
6,064,225 →
Application:
09/045,128 →
An Enhanced Method of Testing Semiconductor Devices Having Nonvolatile Elements
Patent:
5,982,683 →
Application:
09/046,404 →
Offset Voltage Calibration Dac with Reduced Sensitivity to Mismatch Errors
Patent:
6,556,154 →
Application:
09/053,251 →
Method of Testing and Diagnosing Field Programmable Gate Arrays
Patent:
6,108,806 →
Application:
09/059,552 →
Programmable Logic Device
Patent:
6,104,207 →
Application:
09/067,318 →
Internal Tristate Bus with Arbitration Logic
Patent:
6,154,050 →
Application:
09/067,320 →
Combination of Global Clock and Localized Clocks
Patent:
6,133,750 →
Application:
09/069,035 →
Non-Volatile Memory Element for Programmable Logic Applications and Operational Methods Therefor
Patent:
6,002,610 →
Application:
09/069,768 →
Package Migration for Related Programmable Logic Devices
Patent:
6,225,821 →
Application:
09/080,906 →
Programmable Logic Device
Patent:
6,255,847 →
Application:
09/083,205 →
Method and Structure for Dynamic in-System Programming
Patent:
6,304,099 →
Application:
09/083,335 →
Programmable Output Voltage Levels
Patent:
6,066,977 →
Application:
09/083,336 →
Stacked Tunneling Dielectric Technology for Improving Data Retention of Eeprom Cell
Patent:
6,087,696 →
Application:
09/086,437 →
Method and Apparatus for Testing Field Programmable Gate Arrays
Patent:
6,202,182 →
Application:
09/109,123 →
Electrostatic Discharge (Esd) Protection for a 5.0 Volt Compatible Input/Output (I/O) in a 2.5 Volt Semiconductor Process
Patent:
6,028,758 →
Application:
09/114,385 →
Electrostatic Discharge (Esd) Protection for Nmos Pull Up Transistors of a 5.0 Volt Compatible Output Buffer Using 2.5 Volt Process Transistors
Patent:
6,091,595 →
Application:
09/114,717 →
Ballast Resistors with Parallel Stacked Nmos Transistors Used to Prevent Secondary Breakdown During Esd with 2.5 Volt Process Transistors
Patent:
6,043,969 →
Application:
09/114,718 →
Signaling Voltage Range Discriminator
Patent:
6,124,732 →
Application:
09/115,683 →
Flexible Synchronous/and Asynchronous Circuits for a Very High Density Programmable Logic Device
Patent:
6,028,446 →
Application:
09/118,200 →
Data Retention of Eeprom Cell with Shallow Trench Isolation Using Thicker Liner Oxide
Patent:
6,064,105 →
Application:
09/134,174 →
High Speed Line Driver with Direct and Complementary Outputs
Patent:
6,087,854 →
Application:
09/145,793 →
Eeprom Cell with Self-Aligned Tunneling Window
Test Circuits for Testing Inter-Device Fpga Links Including a Shift Register Configured from Fpga Elements to Form a Shift Block Through Said Inter-Device Fpga Links
Patent:
6,347,387 →
Application:
09/169,848 →
Programmable Integrated Circuit Device with Slew Control and Skew Control
Patent:
6,229,336 →
Application:
09/186,917 →
Tileable and Compact Layout for Super Variable Grain Blocks Within Fpga Device
Patent:
6,154,051 →
Application:
09/187,689 →
Semiconductor-Oxide-Semiconductor Capacitor Formed in Integrated Circuit
Patent:
6,228,696 →
Application:
09/187,691 →
High Voltage Switch for Providing Voltages Higher Than 2.5 Volts with Transistors Made Using a 2.5 Volt Process
Patent:
6,169,432 →
Application:
09/188,778 →
Optimization of S/D Annealing to Minimize S/D Shorts in Memory Array
Patent:
6,291,327 →
Application:
09/192,094 →
Reduction of Mechanical Stress in Shallow Trench Isolation Process
Patent:
6,221,733 →
Application:
09/192,096 →
Power Converter with 2.5 Volt Semiconductor Process Components
Patent:
5,912,550 →
Application:
09/196,080 →
Enhanced I/O Control Flexibility for Generating Control Signals
Patent:
6,191,612 →
Application:
09/196,449 →
Eeprom Device Having Improved Data Retention and Operating Method
Patent:
6,009,033 →
Application:
09/198,653 →
Variable Sized Line Driving Amplifiers for Input/Output Blocks (Iobs) in Fpga Integrated Circuits
Patent:
6,218,857 →
Application:
09/198,796 →
Clock Tree Topology
Patent:
6,353,352 →
Application:
09/199,664 →
Method for Forming a Semiconductor Device Having High Reliability Passivation Overlying a Multi-Level Interconnect
Patent:
6,261,944 →
Application:
09/200,395 →
Phase Locked Loop with a Lock Detector
Patent:
6,133,769 →
Application:
09/201,081 →
Eeprom Cell with Tunneling Across Entire Separated Channels
Operational Amplifier with Cmos Transistors Made Using 2.5 Volt Process Transistors
Patent:
6,175,266 →
Application:
09/207,558 →
Efficient Interconnect Network for Use in Fpga Device Having Variable Grain Architecture
Patent:
6,163,168 →
Application:
09/208,203 →
Methods for Configuring Fpga's Having Variable Grain Components for Providing Time-Shared Access to Interconnect Resources
Patent:
6,124,730 →
Application:
09/212,022 →
Methods for Configuring Fpga's Having Variable Grain Blocks and Logic for Providing Time-Shared Access to Interconnect Resources
Patent:
6,100,715 →
Application:
09/212,330 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks Each with Statically and Dynamically Controllable Read Mode
Patent:
6,081,473 →
Application:
09/212,331 →
Method of Forming a Non-Volatile Memory Device
Patent:
6,214,666 →
Application:
09/216,051 →
Methods for Configuring Fpga's Having Variable Grain Blocks and Shared Logic for Providing Symmetric Routing of Result Output to Differently-Directed and Tristateable Interconnect Resources
Patent:
6,204,686 →
Application:
09/216,662 →
Method of Fabricating Programming and Erasing a Dual Pocket Two Sided Program/Erase Non-Volatile Memory Cell
Patent:
6,282,123 →
Application:
09/217,646 →
Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
5,969,992 →
Application:
09/217,647 →
Floating Gate Memory Cell Structure with Programming Mechanism Outside the Read Path
Patent:
6,232,631 →
Application:
09/217,648 →
Eeprom Cell with Tunneling at Separate Edge and Channel Regions
Patent:
6,294,810 →
Application:
09/218,987 →
Avalanche Programmed Floating Gate Memory Cell Structure with Program Element in First Polysilicon Layer
Patent:
6,157,568 →
Application:
09/220,469 →
Avalanche Programmed Floating Gate Memory Cell Structure with Program Element in Polysilicon
Patent:
6,294,809 →
Application:
09/221,360 →
Pmos Avalanche Programmed Floating Gate Memory Cell Structure
Patent:
6,215,700 →
Application:
09/226,702 →
Oxide Formation Process for Manufacturing Programmable Logic Device
Patent:
6,197,638 →
Application:
09/227,981 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks and Interconnect Channel for Broadcasting Address and Control Signals
Patent:
6,181,163 →
Application:
09/235,351 →
Multi-Port Sram Cell Array Having Plural Write Paths Including for Writing Through Addressable Port and Through Serial Boundary Scan
Patent:
6,097,664 →
Application:
09/235,356 →
Fpga Integrated Circuit Having Embedded Sram Memory Blocks with Registered Address and Data Input Sections
Patent:
6,211,695 →
Application:
09/235,615 →
Two Transistor Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
5,999,449 →
Application:
09/239,072 →
Process for Manufacturing Shallow Trenches Filled with Dielectric Material Having Low Mechanical Stress
Patent:
6,297,128 →
Application:
09/240,560 →
Two Transistor Eeprom Cell
Patent:
6,294,811 →
Application:
09/245,813 →
Process for Fabricating a High-Endurance Non-Volatile Memory Device
Patent:
6,255,169 →
Application:
09/255,053 →
Method for Sorting Semiconductor Devices Having a Plurality of Non-Volatile Memory Cells
Patent:
6,075,724 →
Application:
09/255,410 →
Fabrication of Oxide Regions Having Multiple Thicknesses Using Minimized Number of Thermal Cycles
Patent:
6,133,164 →
Application:
09/256,245 →
Fault Tolerant Operation of Field Programmable Gate Arrays
Patent:
6,256,758 →
Application:
09/261,776 →
Semiconductor Device Having a Multi-Layer Metal Interconnect Structure
Patent:
6,075,293 →
Application:
09/263,412 →
Non-Volatile Memory Device Having a High-Reliability Composite Insulaton Layer
Patent:
6,207,989 →
Application:
09/268,897 →
High Voltage Detector to Control a Power Supply Voltage Pump for a 2.5 Volt Semiconductor Process Device
Patent:
6,163,175 →
Application:
09/276,990 →
Band Gap Reference Using a Low Voltage Power Supply
Patent:
6,031,365 →
Application:
09/276,991 →
Avalanche Injection Eeprom Memory Cell with P-Type Control Gate
Patent:
6,326,663 →
Application:
09/277,441 →
Boron Doped Silicon Capacitor Plate
Patent:
6,172,392 →
Application:
09/280,887 →
Angled Nitrogen Ion Implantation for Minimizing Mechanical Stress on Side Walls of an Isolation Trench
Patent:
6,284,626 →
Application:
09/286,830 →
High Dielectric Gate Insulator Process for Nanometer Mosfets
High Speed Logical or Circuit
Patent:
6,265,900 →
Application:
09/288,062 →
Floating Gate Memory Apparatus and Method for Selected Programming Thereof
Patent:
6,424,000 →
Application:
09/310,071 →
Triple-Well Eeprom Cell Using P-Well for Tunneling Across a Channel
Patent:
6,274,898 →
Application:
09/316,241 →
Current-Controlled High Voltage Discharge Scheme
Patent:
6,552,595 →
Application:
09/318,570 →
Electrically Erasable Non-Volatile Memory Cell with Integrated Scram Cell to Reduce Testing Time
Patent:
6,118,693 →
Application:
09/320,389 →
Electrically Erasable Non-Volatile Memory Cell with No Power Dissipation
Patent:
6,067,252 →
Application:
09/320,392 →
Enhanced Macrocell Module for High Density Cpld Architectures
Patent:
6,150,841 →
Application:
09/326,140 →
Scalable Architecture for High Density Cpld's Having Two-Level Hierarachy of Routing Resources
Patent:
6,184,713 →
Application:
09/326,940 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 21, 2019
From: LATTICE SEMICONDUCTOR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049980/0786 →
Release of Security Interest
May 21, 2019
From: JEFFERIES FINANCE LLC
To: LATTICE SEMICONDUCTOR CORPORATION; SILICON IMAGE, INC.; SIBEAM, INC.; DVDO, INC.
Reel/Frame 049827/0326 →