Clock placement for programmable logic devices
View Patent ↗Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.
1. A computer-implemented method comprising:
determining clock resources in a design for a programmable logic device (PLD);
determining available clock resources of the PLD;
determining a flow network model corresponding to the design and the PLD, wherein the flow network model comprises a plurality of levels of vertices disposed between source and sink vertices, a level of vertices adjacent the sink vertex comprises a feedline interconnect vertex for feedline interconnects of the PLD, and each feedline interconnect vertex is coupled to a vertex in an adjacent level of vertices according to a feedline interconnect pattern of the PLD; and
determining a clock resource placement based on the flow network model, wherein the clock resource placement is provided for subsequent design and configuring of a manufactured PLD or programmable logic components.
2. The computer-implemented method of claim 1 , wherein the determining the flow network model comprises:
forming the flow network model comprising the plurality of levels of vertices disposed between the source and sink vertices; and
coupling vertices in the plurality of levels of vertices using edges with unit capacity.
3. The computer-implemented method of claim 1 , wherein:
the determining the flow network model comprises forming the flow network model comprising the plurality of levels of vertices disposed between the source and sink vertices;
a first level of vertices comprises a driver vertex for every clock driver in the design; and
a second level of vertices comprises a source vertex for every clock driver source in the available clock resources of the PLD.
4. The computer-implemented method of claim 3 , wherein:
the forming the flow network model comprises forming a third level of vertices comprising a mirror vertex for every vertex in the second level of vertices.
5. The computer-implemented method of claim 3 , wherein:
the forming the flow network model comprises forming the second level of vertices to include a bypass vertex for every clock driver source with a direct link to the sink vertex in the available clock resources of the PLD.
6. The computer-implemented method of claim 4 , wherein:
each mirror vertex is coupled to a corresponding vertex in the second level of vertices by a single edge to help prevent non-physical solutions to the flow network model.
7. The computer-implemented method of claim 1 , wherein the determining the clock resource placement comprises:
solving the flow network model for a maximum flow through the flow network model; and
determining that a valid clock resource placement exists with respect to the design and the PLD, wherein a valid clock resource placement corresponds to a maximum flow equal to a number of clock drivers in the design.
8. The computer-implemented method of claim 1 , wherein the determining the clock resource placement comprises:
solving the flow network model for a maximum flow through the flow network model; and
determining that no valid clock resource placement exists with respect to the design and the PLD, wherein an invalid clock resource placement corresponds to a maximum flow less than a number of clock drivers in the design.
9. The computer-implemented method of claim 1 , further comprising:
placing specialized PLD components identified in the design; and/or
placing remaining PLD components identified in the design.
10. The computer-implemented method of claim 1 , further comprising:
receiving the design;
synthesizing the design into the plurality of PLD components; and
mapping the plurality of PLD components to the PLD prior to determining the clock resource placement.
11. The computer-implemented method of claim 1 , further comprising:
routing connections to placed PLD components;
generating configuration data to configure physical components of the PLD in accordance with a synthesized design; and
programming the PLD with the configuration data.
12. A system comprising:
a processor; and
a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising:
determining clock resources in a design for a programmable logic device (PLD);
determining available clock resources of the PLD;
determining a flow network model corresponding to the design and the PLD, wherein the flow network model comprises a plurality of levels of vertices disposed between source and sink vertices, a level of vertices adjacent the sink vertex comprises a feedline interconnect vertex for feedline interconnects of the PLD, and each feedline interconnect vertex is coupled to a vertex in an adjacent level of vertices according to a feedline interconnect pattern of the PLD; and
determining a clock resource placement based on the flow network model, wherein the clock resource placement is provided for subsequent design and configuring of a manufactured PLD or programmable logic components.
13. The system of claim 12 , wherein the determining the flow network model comprises:
forming the flow network model comprising the plurality of levels of vertices disposed between the source and sink vertices; and
coupling vertices in the plurality of levels of vertices using edges with unit capacity.
14. The system of claim 12 , wherein:
the determining the flow network model comprises forming the flow network model comprising the plurality of levels of vertices disposed between the source and sink vertices;
a first level of vertices comprises a driver vertex for every clock driver in the design; and
a second level of vertices comprises a source vertex for every clock driver source in the available clock resources of the PLD.
15. The system of claim 14 , wherein:
the forming the flow network model comprises forming a third level of vertices comprising a mirror vertex for every vertex in the second level of vertices.
16. The system of claim 15 , wherein:
each mirror vertex is coupled to a corresponding vertex in the second level of vertices by a single edge to help prevent non-physical solutions to the flow network model.
17. The system of claim 12 , wherein:
the determining the clock resource placement comprises solving the flow network model for a maximum flow through the flow network model; and
a valid solution to the flow network model corresponds to a maximum flow equal to a number of clock drivers in the design.
18. The system of claim 12 , wherein the computer-implemented method further comprises:
placing specialized PLD components identified in the design; and/or
placing remaining PLD components identified in the design.
19. The system of claim 12 , wherein the computer-implemented method further comprises:
receiving the design;
synthesizing the design into the plurality of PLD components; and
mapping the plurality of PLD components to the PLD prior to determining the clock resource placement.
20. The system of claim 12 , wherein the computer-implemented method further comprises:
routing connections to placed PLD components;
generating configuration data to configure physical components of the PLD in accordance with a synthesized design; and
programming the PLD with the configuration data.
21. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:
determining clock resources in a design for a programmable logic device (PLD);
determining available clock resources of the PLD;
determining a flow network model corresponding to the design and the PLD, wherein the flow network model comprises a plurality of levels of vertices disposed between source and sink vertices, a level of vertices adjacent the sink vertex comprises a feedline interconnect vertex for feedline interconnects of the PLD, and each feedline interconnect vertex is coupled to a vertex in an adjacent level of vertices according to a feedline interconnect pattern of the PLD; and
determining a clock resource placement based on the flow network model, wherein the clock resource placement is provided for subsequent design and configuring of a manufactured PLD or programmable logic components.