Patent Assignment
Reel/Frame 044798/0993
Assignment of Assignor's Interest
Recorded: 2018-02-01
Pages: 3
Assignors
CHOURAKI, LAURENT ROBERT
Executed: 2018-01-26
SAINT-MARCEL, LAURENT RENE
Executed: 2018-01-26
SOYER, ALEXANDRE ROGER MAURICE
Executed: 2018-01-26
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System and Method for Electronic Circuit Design Editing Having Adaptive Visual Indicia for Relative Current Loading of Circuit Layout Portions
Patent:
10,482,211 →
Application:
15/886,119 →