Assignment of Assignor's Interest

Recorded: 2018-02-27 Pages: 3

Assignors

KIM, MYONGSEOB

Executed: 2018-02-13

CHANG, CHEANG-WHANG

Executed: 2018-02-27

LIU, HENLEY

Executed: 2018-02-23

Assignee

XILINX, INC.

2100 LOGIC DRIVE, SAN JOSE, CALIFORNIA, 95124

Covered Property (1)

Wafer Edge Partial Die Engineered for Stacked Die Yield

Patent: 10,431,565 →

Application: 15/907,034 →