Patent Assignment
Reel/Frame 045415/0175
Assignment of Assignor's Interest
Recorded: 2018-04-02
Pages: 9
Assignors
WANG, FUYUE
Executed: 2018-03-29
CHEN, LING
Executed: 2018-03-28
WILSON, THOMAS EVAN
Executed: 2018-03-28
ZHANG, JIANYUN
Executed: 2018-03-29
NAVIASKY, ERIC HARRIS
Executed: 2018-04-02
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Dual Path Phase-Locked Loop Circuit
Patent:
10,389,368 →
Application:
15/943,491 →