IP Library › Assignment 046319/0743
Patent Assignment
Reel/Frame 046319/0743

SECURITY INTEREST

Recorded: 2018-06-07 Received: 2018-06-07 Pages: 26
Assignor
NETRONOME SYSTEMS, INC.
Executed: 2018-06-05
Assignee
KREOS CAPITAL V (UK) LIMITED
25 OLD BURLINGTON STREET, LONDON, GBX, W1S 3AN, UNITED KINGDOM
Covered Applications (100)
NETWORK INTERFACE DEVICE THAT ALERTS A MONITORING PROCESSOR IF CONFIGURATION OF A VIRTUAL NID IS CHANGED
App. No. 15/688,937
→
Configurable Mesh Data Bus In An Island-Based Network Flow Processor
App. No. 15/463,857
→
LOW-LEVEL PROGRAMMING LANGUAGE PLUGIN TO AUGMENT HIGH-LEVEL PROGRAMMING LANGUAGE SETUP OF AN SDN SWITCH
App. No. 15/173,653
→
256-Bit Parallel Parser And Checksum Circuit With 1-Hot State Information Bus
App. No. 14/929,275
→
Hash Range Lookup Command
App. No. 14/927,455
→
MAINTAINING BYPASS PACKET COUNT VALUES
App. No. 14/923,457
→
ON-DEMAND GENERATION OF SYSTEM ENTRY PACKET COUNTS
App. No. 14/923,458
→
SIMULTANEOUS SIMULATION OF MULTIPLE BLOCKS USING EFFICIENT PACKET COMMUNICATION TO EMULATE INTER-BLOCK BUSES
App. No. 14/885,978
→
CONTROLLING AN OPTICAL BYPASS SWITCH IN A DATA CENTER BASED ON A NEURAL NETWORK OUTPUT RESULT
App. No. 14/841,723
→
LOADING A FLOW TABLE WITH NEURAL NETWORK DETERMINED INFORMATION
App. No. 14/841,717
→
TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC LOOK-UP, ADD AND LOCK OPERATION
App. No. 14/841,300
→
Script-Controlled Egress Packet Modifier
App. No. 14/818,070
→
SERDES CHANNEL OPTIMIZATION
App. No. 14/731,370
→
GENERATING A FLOW ID BY PASSING PACKET DATA SERIALLY THROUGH TWO CCT CIRCUITS
App. No. 14/726,441
→
Crossbar And An Egress Packet Modifier In An Exact-match Flow Switch
App. No. 14/726,433
→
DISTRIBUTED CREDIT FIFO LINK OF A CONFIGURABLE MESH DATA BUS
App. No. 14/724,820
→
TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND
App. No. 14/724,826
→
Making A Flow ID For An Exact-match Flow Table Using A Programmable Reduce Table Circuit
App. No. 14/726,428
→
RECURSIVE USE OF MULTIPLE HARDWARE LOOKUP STRUCTURES IN A TRANSACTIONAL MEMORY
App. No. 14/724,824
→
Making A Flow ID For An Exact-match Flow Table Using A Byte-Wide Multiplexer Circuit
App. No. 14/726,423
→
TRANSACTIONAL MEMORY THAT SUPPORTS PUT AND GET RING COMMANDS
App. No. 14/724,827
→
Flow Switch IC that Uses Flow IDs and an Exact-match Flow Table
App. No. 14/726,421
→
INTER-PACKET INTERVAL PREDICTION LEARNING ALGORITHM
App. No. 14/690,362
→
SOFTWARE UPDATE METHODOLOGY
App. No. 14/671,951
→
METHOD OF GENERATING SUBFLOW ENTRIES IN AN SDN SWITCH
App. No. 14/634,849
→
SDN PROTOCOL MESSAGE HANDLING WITHIN A MODULAR AND PARTITIONED SDN SWITCH
App. No. 14/634,851
→
FORWARDING MESSAGES WITHIN A SWITCH FABRIC OF AN SDN SWITCH
App. No. 14/634,847
→
METHOD OF DETECTING LARGE FLOWS WITHIN A SWITCH FABRIC OF AN SDN SWITCH
App. No. 14/634,848
→
EFFICIENT COMPLEX NETWORK TRAFFIC MANAGEMENT IN A NON-UNIFORM MEMORY SYSTEM
App. No. 14/631,784
→
TRANSACTIONAL MEMORY THAT PERFORMS AN ALUT 32-BIT LOOKUP OPERATION
App. No. 14/631,748
→
TRANSACTIONAL MEMORY THAT SUPPORTS A PUT WITH LOW PRIORITY RING COMMAND
App. No. 14/631,804
→
PACKET ORDERING SYSTEM USING AN ATOMIC TICKET RELEASE COMMAND OF A TRANSACTIONAL MEMORY
App. No. 14/611,231
→
Distributed Packet Ordering System Having Separate Worker And Output Processors
App. No. 14/611,224
→
USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE
App. No. 14/591,003
→
RETURN AVAILABLE PPI CREDITS COMMAND
App. No. 14/590,920
→
TRANSACTIONAL MEMORY THAT PERFORMS A TCAM 32-BIT LOOKUP OPERATION
App. No. 14/588,280
→
TRANSACTIONAL MEMORY THAT PERFORMS A PMM 32-BIT LOOKUP OPERATION
App. No. 14/588,342
→
Flow Control Using A Local Event Ring In An Island-Based Network Flow Processor
App. No. 14/588,084
→
STAGGERED ISLAND STRUCTURE IN AN ISLAND-BASED NETWORK FLOW PROCESSOR
App. No. 14/556,147
→
RECURSIVE LOOKUP WITH A HARDWARE TRIE STRUCTURE THAT HAS NO SEQUENTIAL LOGIC ELEMENTS
App. No. 14/556,135
→
COMPARTMENTALIZATION OF THE USER NETWORK INTERFACE TO A DEVICE
App. No. 14/551,057
→
FLOW KEY LOOKUP INVOLVING MULTIPLE SIMULTANEOUS CAM OPERATIONS TO IDENTIFY HASH VALUES IN A HASH BUCKET
App. No. 14/537,514
→
UNIQUE PACKET MULTICAST PACKET READY COMMAND
App. No. 14/530,759
→
Intelligent Packet Data Register File That Prefetches Data For Future Instruction Execution
App. No. 14/530,763
→
Intelligent Packet Data Register File That Stalls Picoengine And Retrieves Data From A Larger Buffer
App. No. 14/530,762
→
UNICAST PACKET READY COMMAND
App. No. 14/530,760
→
Picoengine Instruction That Controls An Intelligent Packet Data Register File Prefetch Function
App. No. 14/530,764
→
IDENTICAL PACKET MULTICAST PACKET READY COMMAND
App. No. 14/530,758
→
SLICE-BASED INTELLIGENT PACKET DATA REGISTER FILE
App. No. 14/530,765
→
In-Flight Packet Processing
App. No. 14/530,599
→
REGISTERED FIFO
App. No. 14/527,550
→
SPLIT PACKET TRANSMISSION DMA ENGINE
App. No. 14/527,642
→
MINIPACKET FLOW CONTROL
App. No. 14/521,435
→
GLOBAL RANDOM EARLY DETECTION PACKET DROPPING BASED ON AVAILABLE MEMORY
App. No. 14/507,621
→
PACKET STORAGE DISTRIBUTION BASED ON AVAILABLE MEMORY
App. No. 14/507,643
→
SIMULTANEOUS QUEUE RANDOM EARLY DETECTION DROPPING AND GLOBAL RANDOM EARLY DETECTION DROPPING SYSTEM
App. No. 14/507,652
→
INSTANTANEOUS RANDOM EARLY DETECTION PACKET DROPPING WITH DROP PRECEDENCE
App. No. 14/507,602
→
ADDRESSLESS MERGE COMMAND WITH DATA ITEM IDENTIFIER
App. No. 14/492,013
→
CHAINED CPP COMMAND
App. No. 14/492,015
→
PACKET ENGINE THAT USES PPI ADDRESSING
App. No. 14/464,690
→
CPP BUS TRANSACTION VALUE HAVING A PAM/LAM SELECTION CODE FIELD
App. No. 14/464,697
→
PPI DE-ALLOCATE CPP BUS COMMAND
App. No. 14/464,700
→
PPI ALLOCATION REQUEST AND RESPONSE FOR ACCESSING A MEMORY SYSTEM
App. No. 14/464,692
→
GENERATING A HASH USING S-BOX NONLINEARIZING OF A REMAINDER INPUT
App. No. 14/448,980
→
DDR Retiming Circuit
App. No. 14/448,841
→
PICOENGINE HAVING A HASH GENERATOR WITH REMAINDER INPUT S-BOX NONLINEARIZING
App. No. 14/448,906
→
MULTI-PROCESSOR WITH EFFICIENT SEARCH KEY PROCESSING
App. No. 14/326,367
→
ISLAND-BASED NETWORK FLOW PROCESSOR WITH EFFICIENT SEARCH KEY PROCESSING
App. No. 14/326,381
→
EFFICIENT SEARCH KEY PROCESSING METHOD
App. No. 14/326,388
→
EFFICIENT SEARCH KEY CONTROLLER WITH STANDARD BUS INTERFACE, EXTERNAL MEMORY INTERFACE, AND INTERLAKEN LOOKASIDE INTERFACE
App. No. 14/326,372
→
MERGING PCP FLOWS AS THEY ARE ASSIGNED TO A SINGLE VIRTUAL CHANNEL
App. No. 14/321,732
→
REORDERING PCP FLOWS AS THEY ARE ASSIGNED TO VIRTUAL CHANNELS
App. No. 14/321,744
→
HIGH-SPEED DEQUEUING OF BUFFER IDS IN FRAME STORING SYSTEM
App. No. 14/321,756
→
INVERSE PCP FLOW REMAPPING FOR PFC PAUSE FRAME GENERATION
App. No. 14/321,762
→
SKIP INSTRUCTION TO SKIP A NUMBER OF INSTRUCTIONS ON A PREDICATE
App. No. 14/311,222
→
MULTI-PROCESSOR SYSTEM HAVING TRIPWIRE DATA MERGING AND COLLISION DETECTION
App. No. 14/311,217
→
PROCESSOR HAVING A TRIPWIRE BUS PORT AND EXECUTING A TRIPWIRE INSTRUCTION
App. No. 14/311,212
→
EFFICIENT CONDITIONAL INSTRUCTION HAVING COMPANION LOAD PREDICATE BITS INSTRUCTION
App. No. 14/311,225
→
TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND
App. No. 14/287,012
→
TABLE FETCH PROCESSOR INSTRUCTION USING TABLE NUMBER TO BASE ADDRESS TRANSLATION
App. No. 14/267,342
→
POP STACK ABSOLUTE INSTRUCTION
App. No. 14/267,362
→
KICK-STARTED RUN-TO-COMPLETION PROCESSING METHOD THAT DOES NOT INVOLVE AN INSTRUCTION COUNTER
App. No. 14/267,329
→
KICK-STARTED RUN-TO-COMPLETION PROCESSOR HAVING NO INSTRUCTION COUNTER
App. No. 14/267,298
→
PACKET PREDICTION IN A MULTI-PROTOCOL LABEL SWITCHING NETWORK USING OPENFLOW MESSAGING
App. No. 14/263,999
→
PACKET PREDICTION IN A MULTI-PROTOCOL LABEL SWITCHING NETWORK USING OPERATION, ADMINISTRATION, AND MAINTENANCE (OAM) MESSAGING
App. No. 14/264,003
→
PICOENGINE MULTI-PROCESSOR WITH TASK ASSIGNMENT
App. No. 14/251,592
→
PICOENGINE MULTI-PROCESSOR WITH POWER CONTROL MANAGEMENT
App. No. 14/251,599
→
CHAINED-INSTRUCTION DISPATCHER
App. No. 14/231,028
→
INSTANTANEOUS RANDOM EARLY DETECTION PACKET DROPPING
App. No. 14/205,824
→
GUARANTEED IN-ORDER PACKET DELIVERY
App. No. 14/184,455
→
NETWORK INTERFACE DEVICE THAT ALERTS A MONITORING PROCESSOR IF CONFIGURATION OF A VIRTUAL NID IS CHANGED
App. No. 14/172,851
→
TRANSACTIONAL MEMORY THAT PERFORMS A PROGRAMMABLE ADDRESS TRANSLATION IF A DAT BIT IN A TRANSACTIONAL MEMORY WRITE COMMAND IS SET
App. No. 14/172,856
→
TRANSACTIONAL MEMORY THAT IS PROGRAMMABLE TO OUTPUT AN ALERT IF A PREDETERMINED MEMORY WRITE OCCURS
App. No. 14/172,862
→
NETWORK INTERFACE DEVICE THAT MAPS HOST BUS WRITES OF CONFIGURATION INFORMATION FOR VIRTUAL NIDS INTO A SMALL TRANSACTIONAL MEMORY
App. No. 14/172,844
→
AUTOMATON HARDWARE ENGINE EMPLOYING MEMORY-EFFICIENT TRANSITION TABLE INDEXING
App. No. 14/151,643
→
COMMAND-DRIVEN NFA HARDWARE ENGINE THAT ENCODES MULTIPLE AUTOMATONS
App. No. 14/151,666
→
DEDICATED EGRESS FAST PATH FOR NON-MATCHING PACKETS IN AN OPENFLOW SWITCH
App. No. 14/151,730
→
TRANSACTIONAL MEMORY HAVING LOCAL CAM AND NFA RESOURCES
App. No. 14/151,677
→
NFA BYTE DETECTOR
App. No. 14/151,688
→
NFA COMPLETION NOTIFICATION
App. No. 14/151,699
→