IP Library Assignment 046371/0471
Patent Assignment
Reel/Frame 046371/0471

Assignment of Assignor's Interest

Recorded: 2018-07-17 Pages: 5
Assignors
LILAK, AARON D.
Executed: 2018-06-28
DEWEY, GILBERT
Executed: 2018-06-18
HUANG, CHENG-YING
Executed: 2018-06-29
JEZEWSKI, CHRISTOPHER
Executed: 2018-07-10
MANNEBACH, EHREN
Executed: 2018-06-29
MEHANDRU, RISHABH
Executed: 2018-06-28
MORROW, PATRICK
Executed: 2018-06-28
MURTHY, ANAND S.
Executed: 2018-07-12
PHAN, ANH
Executed: 2018-07-10
RACHMADY, WILLY
Executed: 2018-07-10
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Interconnect Techniques for Electrically Connecting Source/Drain Regions of Stacked Transistors
Application: 16/024,058 →
Publication: US 2020/0006329