Patent Assignment
Reel/Frame 047014/0777
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2018-07-06
Received: 2018-07-06
Pages: 22
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2018-06-26
Assignee
INNOVATIVE FOUNDRY TECHNOLOGIES LLC
40 PLEASANT STREET, SUITE 208, PORTSMOUTH, NH, 03801, UNITED STATES
Covered Applications
(59)
INTEGRATED CIRCUIT WITH METAL AND SEMI-CONDUCTING GATE
App. No. 13/644,387
→
METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION
App. No. 13/176,614
→
TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY
App. No. 12/821,308
→
STRESS ENHANCED TRANSISTOR
App. No. 12/644,882
→
CONTACT TRENCHES FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS
App. No. 12/469,972
→
SEMICONDUCTOR DEVICES HAVING FACETED SILICIDE CONTACTS, AND RELATED FABRICATION METHODS
App. No. 12/249,570
→
CMOS CIRCUIT HAVING A TENSILE STRESS LAYER OVERLYING AN NMOS TRANSISTOR AND OVERLAPPING A PORTION OF A COMPRESSIVE STRESS LAYER.
App. No. 12/199,659
→
SEMICONDUCTOR CIRCUIT INCLUDING A LONG CHANNEL DEVICE AND A SHORT CHANNEL DEVICE
App. No. 12/181,180
→
METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION
App. No. 12/176,866
→
HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE
App. No. 12/131,332
→
SEMICONDUCTOR CHIP WITH STRATIFIED UNDERFILL
App. No. 11/849,545
→
INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE
App. No. 11/611,856
→
STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION
App. No. 11/611,784
→
TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY
App. No. 11/567,268
→
STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION
App. No. 11/562,209
→
METHOD FOR FORMING EMBEDDED STRAINED DRAIN/SOURCE REGIONS BASED ON A COMBINED SPACER AND CAVITY ETCH PROCESS
App. No. 11/559,462
→
METHOD OF INCREASING THE ETCH SELECTIVITY IN A CONTACT STRUCTURE OF SEMICONDUCTOR DEVICES
App. No. 11/538,111
→
FABRICATION METHODS FOR STRESS ENHANCED CMOS CIRCUITS
App. No. 11/532,753
→
FORMATION OF ABRUPT JUNCTIONS IN DEVICES BY USING SILICIDE GROWTH DOPANT SNOWPLOW EFFECT
App. No. 11/422,811
→
COMPOSITE BARRIER LAYERS WITH CONTROLLED COPPER INTERFACE SURFACE ROUGHNESS
App. No. 11/376,190
→
TECHNIQUE FOR FORMING A CONTACT INSULATION LAYER WITH ENHANCED STRESS TRANSFER EFFICIENCY
App. No. 11/288,673
→
SYSTEM AND METHOD FOR IMPROVING RELIABILITY IN A SEMICONDUCTOR DEVICE
App. No. 11/186,969
→
DECOUPLING CAPACITOR DENSITY WHILE MAINTAINING CONTROL OVER ACLV REGIONS ON A SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 11/174,713
→
TECHNIQUE FOR CREATING DIFFERENT MECHANICAL STRAIN IN DIFFERENT CHANNEL REGIONS BY FORMING AN ETCH STOP LAYER STACK HAVING DIFFERENTLY MODIFIED INTRINSIC STRESS
App. No. 11/150,635
→
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE
App. No. 11/119,660
→
SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION
App. No. 11/072,142
→
COMPOSITE TANTALUM NITRIDE/TANTALUM COPPER CAPPING LAYER
App. No. 10/934,511
→
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
App. No. 10/915,638
→
METHOD FOR FORMING A FIELD EFFECT TRANSISTOR HAVING A HIGH-K GATE DIELECTRIC
App. No. 10/899,955
→
IN-SITU NITRIDE/OXYNITRIDE PROCESSING WITH REDUCED DEPOSITION SURFACE PATTERN SENSITIVITY
App. No. 10/887,836
→
LOW POWER PRE-SILICIDE PROCESS IN INTEGRATED CIRCUIT TECHNOLOGY
App. No. 10/859,286
→
STRAINED CHANNEL FINFET
App. No. 10/833,112
→
METHOD OF FORMING COMPOSITE BARRIER LAYERS WITH CONTROLLED COPPER INTERFACE SURFACE ROUGHNESS
App. No. 10/811,866
→
LOW STRESS SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
App. No. 10/756,023
→
FORMATION OF ABRUPT JUNCTIONS IN DEVICES BY USING SILICIDE GROWTH DOPANT SNOWPLOW EFFECT
App. No. 10/727,999
→
CONFORMAL BARRIER LINER IN AN INTEGRATED CIRCUIT INTERCONNECT
App. No. 10/672,103
→
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT WITH LOW SOLUBILITY METAL-CONDUCTOR INTERCONNECT CAP
App. No. 10/672,126
→
METHOD FOR FORMING A FIELD EFFECT TRANSISTOR HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE
App. No. 10/618,273
→
FINFET GATE FORMATION USING REVERSE TRIM AND OXIDE POLISH
App. No. 10/459,589
→
METHOD FOR FORMING MULTIPLE FINS IN A SEMICONDUCTOR DEVICE
App. No. 10/429,780
→
DUAL DAMASCENE INTEGRATION SCHEME FOR PREVENTING COPPER CONTAMINATION OF DIELECTRIC LAYER
App. No. 10/422,784
→
STRAINED CHANNEL FINFET
App. No. 10/349,042
→
METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT
App. No. 10/284,651
→
SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION AND METHOD FOR FABRICATING THE SAME
App. No. 10/282,980
→
METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT."
App. No. 10/236,200
→
METHOD FOR MANUFACTURING A SCRIBE SEAL STRUCTURE
App. No. 10/177,336
→
CONFORMAL BARRIER LINER IN AN INTEGRATED CIRCUIT INTERCONNECT
App. No. 10/165,510
→
SEMICONDUCTOR DEVICE AND FABRICATION TECHNIQUE USING A HIGH-K LINER FOR SPACER ETCH STOP
App. No. 10/163,930
→
SEMICONDUCTOR PACKAGING APPAATS FOR CONTROLLING DIE ATTACH FILLET HEIGHT TO REDUCE DIE SHEAR STRESS
App. No. 10/053,994
→
INTEGRATED CIRCUIT WITH LOW SOLUBILITY METAL-CONDUCTOR INTERCONNECT CAP
App. No. 10/016,024
→
INTEGRATED CIRCUIT INTERCONNECT SHUNT LAYER
App. No. 09/905,479
→
INTEGRATION OF ORGANIC FILL FOR DUAL DAMASCENE PROCESS
App. No. 09/892,750
→
MOSFET WITH SIGE SOURCE/DRAIN REGIONS AND EPITAXIAL GATE DIELECTRIC
App. No. 09/877,906
→
SELF-ALIGNED CONDUCTIVE PLUGS IN A SEMICONDUCTOR DEVICE
App. No. 09/826,185
→
METHOD AND APPARATUS FOR SHIELDING ELECTROMAGNETIC EMISSIONS FROM AN INTEGRATED CIRCUIT
App. No. 09/824,148
→
TRANSISTOR DEVICE HAVING AN ENHANCED WIDTH DIMENSION AND A METHOD OF MAKING SAME
App. No. 09/812,521
→
DUAL DAMASCENE INTEGRATION SCHEME FOR PREVENTING COPPER CONTAMINATION OF DIELECTRIC LAYER
App. No. 09/793,993
→
CU DAMASCENE INTERCONNECTIONS USING BARRIER/CAPPING LAYER
App. No. 09/783,619
→
SEMICONDUCTOR DEVICES UTILIZING DIFFERENTLY COMPOSED METAL-BASED IN-LAID GATE ELECTRODES
App. No. 09/781,436
→