Patent Assignment
Reel/Frame 047617/0907
Assignment of Assignor's Interest
Recorded: 2018-11-29
Pages: 18
Assignors
JEONG, SEUNG-GYU
Executed: 2018-11-21
HONG, DO-SUN
Executed: 2018-11-21
KWON, JUNG-HYUN
Executed: 2018-11-21
SHIN, WON-GYU
Executed: 2018-11-21
Assignee
SK HYNIX INC.
2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF
Covered Property
(1)
Delay Circuit and Write and Read Latency Control Circuit of Memory, and Signal Delay Method Thereof