Patent Assignment
Reel/Frame 047663/0014
Assignment of Assignor's Interest
Recorded: 2018-12-03
Pages: 4
Assignors
WU, WEI
Executed: 2018-11-30
SHEN, ZHENLEI
Executed: 2018-11-29
CHEN, ZHENGANG
Executed: 2018-11-29
Assignee
MICRON TECHNOLOGY, INC.
8000 SOUTH FEDERAL WAY, BOISE, IDAHO, 83716-9632
Covered Property
(1)
Failure-Tolerant Error Correction Layout for Memory Sub-Systems
Related Assignments
(4)
Other recorded transfers of the patent in this record — the chain of ownership.
Supplement No. 11 to Patent Security Agreement
Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
Supplement No. 2 to Patent Security Agreement
Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
Release of Security Interest
Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
Release of Security Interest
Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →