Patent Assignment
Reel/Frame 048082/0860
Supplement No. 11 to Patent Security Agreement
Recorded: 2019-01-16
Pages: 29
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2019-01-15
Assignee
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(376)
Pixel with Strained Silicon Layer for Improving Carrier Mobility and Blue Response in Imagers
Electronic Systems and Methods of Forming Semiconductor Constructions
Microelectronic Device Packages, Stacked Microelectronic Device Packages, and Methods for Manufacturing Microelectronic Devices
Methods of Forming One or More Covered Voids in a Semiconductor Substrate
Recycled Version Number Values in Flash Memory
Encoding Data in a Modified-Memory System
Methods of Forming a Semiconductor Device Using Block Copolymer Materials
Memory Devices Having Special Mode Access Using a Serial Message
Systems and Methods to Determine Kinematical Parameters
Methods of Command Based and Current Limit Controlled Memory Device Power Up
Memory Systems for Data Collection and Compression in a Storage Device
Methods of Removing Particles from Over Semiconductor Substrates
Devices, Systems, and Methods to Synchronize Simultaneous Dma Parallel Processing of a Single Data Stream by Multiple Devices
Methods and Apparatuses for Reducing Power Consumption in a Pattern Recognition Processor
Line Termination Methods
Unaligned Data Coalescing
Electrically Conductive Laminate Structures
Programmable Device, Hierarchical Parallel Machines, and Methods for Providing State Information
Solid State Lighting Devices Having Improved Color Uniformity and Associated Methods
Solid State Lighting Devices with Improved Current Spreading and Light Extraction and Associated Methods
Methods, Apparatuses, and Circuits for Programming a Memory Device
Apparatus and Methods Including Source Gates
Methods, Articles, and Devices for Pulse Adjustments to Program a Memory Cell
Memories and Methods to Provide Configuration Information to Controllers
Circuits, Apparatuses, and Methods for Frequency Division
Configurable Operating Mode Memory Device and Methods of Operation
Methods of Operating a Memory Device Comparing Input Data to Data Stored in Memory Cells Coupled to a Data Line
Methods of Operating a Memory Device Comparing Input Data to Data Stored in Memory Cells Coupled to a Data Line
Memory Cells, Semiconductor Devices Including the Memory Cells, and Methods of Operation
Semiconductor Devices and Related Methods
Memory Having Memory Cell String and Coupling Components
Patent:
10,484,718 →
Application:
16/197,174 →
Stacked Semiconductor Die Assemblies with Multiple Thermal Paths and Associated Systems and Methods
Apparatuses and Methods Using Negative Voltages in Part of Memory Write, Read, and Erase Operations
Apparatuses and Methods for Memory Operations Having Variable Latencies
Apparatuses and Methods Involving Accessing Distributed Sub-Blocks of Memory Cells
Memories Having Select Devices Between Access Lines and in Memory Cells
Devices, Systems and Methods for Electrostatic Force Enhanced Semiconductor Bonding
Apparatuses, Circuits, and Methods for Biasing Signal Lines
Electronic Devices and Related Electronic Systems
Apparatuses and Methods for Selective Row Refreshes
Apparatuses and Methods for Selective Row Refreshes
Array Of Recessed Access Gate Lines
Apparatuses and Method for Over-Voltage Event Protection
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Semiconductor Device Structures Including Silicon-Containing Dielectric Materials
Memory Cell with Independently-Sized Elements
Methods of Forming Structures
Data Storage Management
Command Queuing
Memory Systems and Memory Programming Methods
Apparatuses, Memories, and Methods for Address Decoding and Selecting an Access Line
Methods of Operating Memory Devices and Apparatuses
Semiconductor Device Packages with Direct Electrical Connections and Related Methods
Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices
Semiconductor Device Test Apparatuses Comprising at Least One Test Site Having an Array of Pockets
Self-Accumulating Exclusive or Program
Apparatuses and Methods for Reducing Read Disturb
Apparatuses Including Multiple Read Modes and Methods for Same
Semiconductor Die Assemblies with Heat Sink and Associated Systems and Methods
Methods of Forming Memory Cells and Semiconductor Devices
Apparatuses and Methods for Performing an Exclusive or Operation Using Sensing Circuitry
Semiconductor Device Including Sensor
Sort Operation in Memory
Multiple Endianness Compatibility
Scalable Memory System Protocol Supporting Programmable Number of Levels of Indirection
Dynamic Adjustment of Memory Cell Digit Line Capacitance
Vector Population Count Determination via Comparison Iterations in Memory
Apparatus Configured to Program Memory Cells Using an Intermediate Level for Multiple Data States
Cell-Based Reference Voltage Generation
Face Down Dual Sided Chip Scale Memory Package
Apparatuses and Methods for Memory Device as a Store for Block Program Instructions
Devices and Apparatuses Including Asymmetric Ferroelectric Materials, and Related Methods
Apparatuses and Methods for Shift Decisions
Logical Address History Management in Memory Device
Methods and Devices for Reducing Array Size and Complexity in Automata Processors
Gate Stacks
Charge Extraction from Ferroelectric Memory Cell
Charge Extraction from Ferroelectric Memory Cell
Methods of Operating Microelectronic Devices Including a Controller
Apparatuses and Methods for Asymmetric Input/Output Interface for a Memory
Solid State Storage Device with Command and Control Access
Ground Reference Scheme for a Memory Cell
Apparatuses and Methods for Temperature Independent Oscillators
Apparatuses and Methods for Chip Identification in a Memory Package
Apparatuses and Methods for Current Limitation in Threshold Switching Memories
Target Architecture Determination
Arrays of Cross-Point Memory Structures, and Methods of Forming Arrays of Cross-Point Memory Structures
Apparatuses and Methods for Scalable Memory
Non-Volatile Memory Module Architecture to Support Memory Error Correction
Non-Volatile Memory Including Selective Error Correction
Methods and Apparatuses for Signal Translation in a Buffered Memory
Methods of Forming Semiconductor Devices
Error Code Calculation on Sensing Circuitry
Apparatuses and Methods for Multiple Address Registers for a Solid State Device
Apparatuses and Methods for Level Shifting
Memory Device with Write Data Bus Control
Writing to Cross-Point Non-Volatile Memory
Error Correction Code (Ecc) Operations in Memory
Ferroelectric Memory Cell Apparatuses and Methods of Operating Ferroelectric Memory Cells
Charge Sharing Between Memory Cell Plates Using a Conductive Path
Charge Mirror-Based Sensing for Ferroelectric Memory
Ferroelectric Memory Cell Recovery
Accessing Data in Memory
Apparatuses for Reducing Off State Leakage Currents
Logic Component Switch
System and Method for Individual Addressing
Package-On-Package Semiconductor Device Assemblies Including One or More Windows and Related Methods and Packages
Data Transfer Techniques for Multiple Devices on a Shared Bus
Methods of Forming Semiconductor Device Structures
Apparatuses and Methods for Random Number Generation
Element Value Comparison in Memory
Apparatuses and Methods for Staircase Code Encoding and Decoding for Storage Devices
Integrated Structures Including Material Containing Silicon, Nitrogen, and at Least One of Carbon, Oxygen, Boron and Phosphorus
Adaptive Routing to Avoid Non-Repairable Memory and Logic Defects on Automata Processor
Semiconductor Devices Including Liners, and Related Systems
Managing Host Communication with a Regulator in a Low Power Mode
Dynamic Reference Voltage Determination
Vertical Two-Transistor Single Capacitor Memory Cells and Memory Arrays
Error Correction Code (Ecc) Operations in Memory
Vertical 2T-2C Memory Cells and Memory Arrays
Apparatuses Having Memory Strings Compared to One Another Through a Sense Amplifier
Circuit and Layout for Single Gate Type Precharge Circuit for Data Lines in Memory Device
Memory Devices and Systems with Security Capabilities
Application:
16/164,332 →
Publication:
US US20190050297A1
Apparatus and Method of Power Transmission Sensing for Stacked Devices
Obfuscation-Enhanced Memory Encryption
Apparatuses and Methods for High Speed Writing Test Mode for Memories
Apparatus and Methods for in Data Path Compute Operations
Active Boundary Quilt Architecture Memory
Identifying Asynchronous Power Loss
Apparatuses and Methods for Providing Reference Voltages
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
Chalcogenide Memory Device Components and Composition
Cell Disturb Prevention Using a Leaker Device to Reduce Excess Charge from an Electronic Device
Periphery Fill and Localized Capacitance
Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Extending Conductor Laterally Between A Pair Of Structures
Methods of Sketch-Based Memory Management and Memory Devices Utilizing the Same
Methods of Bit-Flagged Sketch-Based Memory Management and Memory Devices Utilizing the Same
Memory Cells and Memory Arrays
Memory Device Including Voids Between Control Gates
Scan Chain Operations
Apparatuses and Methods for in-Memory Operations
Three-Dimensional Memory Devices, and Related Methods and Electronic Systems
Refresh in Non-Volatile Memory
Dual Mode Ferroelectric Memory Cell Operation
Dual Mode Ferroelectric Memory Cell Operation
Memory Device Including Mixed Non-Volatile Memory Cell Types
Memory Management
Memory Device Including Pass Transistors in Memory Tiers
Mixed Cross Point Memory
Mixed Cross Point Memory
Input Buffer Circuit
Apparatus and Methods for via Connection with Reduced via Currents
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
Memory Device with Dynamic Storage Mode Control
Wiring with External Terminal
Offset Cancellation for Latching in a Memory Device
Memory Arrays, and Methods of Forming Memory Arrays
Patent:
10,242,726 →
Application:
16/180,542 →
Apparatuses and Methods for Configurable Command and Data Input Circuits for Semiconductor Memories
Memory Cells Having Resistors and Formation of the Same
Mitigating Line-to-Line Capacitive Coupling in a Memory Die
Methods of Forming Semiconductor Device Structures
Methods of Forming Staircase Structures
Characterization of Decision Feedback Equalizer Taps
A Device Module Having a Plurality of Dies Electrically Connected by Posts
Responding to Power Loss
Semiconductor Structures Including Memory Materials Substantially Encapsulated with Dielectric Materials
Semiconductor Constructions Comprising Dielectric Material, and Methods of Forming Dielectric Fill Within Openings Extending into Semiconductor Constructions
Time-Based Access of a Memory Cell
Time-Based Access of a Memory Cell
Semiconductor Structures, Memory Cells and Devices Comprising Ferroelectric Materials, Systems Including Same, and Related Methods
Semiconductor Devices, and Related Control Logic Assemblies, Electronic Systems, and Methods
Program Operations in Memory
Asymmetrical Multi-Gate String Driver for Memory Device
Methods of Forming a Memory Structure
Multifunctional Memory Cells
Electronic Devices Having Tapered Edge Walls
Methods of Processing Semiconductor Devices
Reflow Protection
Dqs-Offset and Read-Rtt-Disable Edge Control
Semiconductor Devices with Package-Level Configurability
Data Output for High Frequency Domain
Dynamic Termination Edge Control
Systems and Methods for Frequency Mode Detection and Implementation
Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures
Analog Multiplexing Scheme for Decision Feedback Equalizers
Voltage Reference Computations for Memory Decision Feedback Equalizers
Power Reduction Technique During Read/Write Bursts
Multi-Phase Clock Division
Apparatuses and Methods for Providing Bias Signals in a Semiconductor Device
Pseudo-Non-Volatile Memory Cells
Apparatuses and Methods for Providing Frequency Divided Clocks
3D Memory Device Including Shared Select Gate Connections Between Memory Blocks
Methods of Determining Host Clock Frequency for Run Time Optimization of Memory and Memory Devices Employing the Same
Memory Devices with Programmable Latencies and Methods for Operating the Same
Systems and Methods for Maintaining Refresh Operations of Memory Banks Using a Shared Address Path
Methods of Synchronizing Memory Operations and Memory Systems Employing the Same
I/O Buffer Offset Mitigation
Internal Clock Distortion Calibration Using Dc Component Offset of Clock Signal
Namespace Change Propagation in Non-Volatile Memory Devices
Methods for Processing Semiconductor Dice and Fabricating Assemblies Incorporating Same
Uncorrectable Ecc
Increased Nand Performance Under High Thermal Conditions
Optimized Scan Interval
Systems and Methods for Initializing Bandgap Circuits
Electronic Device with a Fuse Read Mechanism
Data Strobe Gating
Patent:
10,283,188 →
Application:
16/175,676 →
Output Impedance Calibration for Signaling
Artificial Neural Network Integrity Verification
Single Word Line Gain Cell with Complementary Read Write Channel
Application:
62/785,163 →
Methods of Forming an Apparatus, and Related Apparatuses and Electronic Systems
Memory Device and Managed Memory System with Wireless Debug Communication Port and Methods for Operating the Same
Application:
16/231,267 →
Publication:
US US20200204991A1
Cross Point Array Memory in a Non-Volatile Dual in-Line Memory Module
Memory Arrays And Methods Used In Forming A Memory Array
Decoder Circuit
Leakage Compensation for Memory Arrays
Semiconductor Device Performing Row Hammer Refresh Operation
Application:
16/208,217 →
Memory Cells Configured to Generate Weighted Inputs for Neural Networks
Electrical Device with Test Pads Encased Within the Packaging Material
Changing of Error Correction Codes Based on the Wear of a Memory Sub-System
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
Application:
62/768,477 →
Construction Of Integrated Circuitry, DRAM Circuitry, A Method Of Forming A Conductive Line Construction, A Method Of Forming Memory Circuitry, And A Method Of Forming DRAM Circuitry
Patent:
10,607,996 →
Application:
16/232,634 →
Power Loss Protection in Memory Sub-Systems
Failure-Tolerant Error Correction Layout for Memory Sub-Systems
Data Integrity Protection for Relocating Data in a Memory System
Physical Unclonable Function with Nand Memory Array
Monotonic Counters in Memories
Devices Including Conductive Interconnect Structures, Related Electronic Systems, and Related Methods
Apparatus and Methods for Programming Memory Cells Responsive to an Indication of Age of the Memory Cells
Apparatuses and Methods for Multi-Bank and Multi-Pump Refresh Operations
Apparatuses and Methods for Refresh Operations Including Multiple Refresh Activations
Methods and System with Dynamic Ecc Voltage and Frequency
Apparatuses for Decreasing Write Pull-Up Time and Methods of Use
Age-Based Refresh of Firmware
Apparatuses and Methods for Arranging Through-Silicon Vias and Pads in a Semiconductor Device
Apparatuses and Methods Including Configurable Logic Circuits and Layout Thereof
Patent:
10,411,708 →
Application:
16/228,156 →
Management of Power State Transitions of a Memory Sub-System
Apparatuses and Methods for Refresh Operations in Semiconductor Memories
Apparatuses and Methods for Multi-Bank Refresh Timing
Patent:
10,593,392 →
Application:
16/226,525 →
Secure Communication for Log Reporting in Memory Sub-Systems
Application:
16/228,203 →
Publication:
US US20200202017A1
Apparatus and Methods for Determining Data States of Memory Cells
Application:
62/785,731 →
Holdup Self-Tests for Power Loss Operations on Memory Systems
Degradation Signaling for a Memory Device
Parking Infrastructure Powered by a Decentralized, Distributed Database
Automated Verification Code Generation Based on a Hardware Design and Design Data
Application:
62/769,839 →
Bad Block Management for Memory Sub-Systems
Reset Interception to Avoid Data Loss in Storage Device Resets
Low Cost and Low Latency Logical Unit Erase
Apparatuses and Methods for Staggered Timing of Targeted Refresh Operations
Application:
16/230,300 →
Binary Parallel Adder and Multiplier
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
Application:
62/743,381 →
Nand Reliability Improvements
Application:
62/787,077 →
Accelerated Access to Computations Results Generated from Data Stored in Memory Devices
Application:
16/158,558 →
Publication:
US US20200117449A1
Parallel Memory Access and Computation in Memory Devices
Management of Event Log Information of a Memory Sub-System
Feedback for Multi-Level Signaling in a Memory Device
Using a Common Pool of Blocks for User Data and a System Data Structure
Hybrid Logical to Physical Caching Scheme
Application:
62/787,043 →
File Creation with Requester-Specified Backing
Providing Information of a Controller Memory Buffer of a Memory Sub-System to a Host System
Application:
62/752,766 →
Providing Information for a Controller Memory Buffer Elasticity Status of a Memory Sub-System to a Host System
Sequential Data Optimized Sub-Regions in Storage Devices
Apparatuses and Methods for Distributed Targeted Refresh Operations
Interposers for Microelectronic Devices
Application:
62/772,291 →
Using a Second Content-Addressable Memory to Manage Memory Burst Accesses in Memory Sub-Systems
Interruption of Program Operations at a Memory Sub-System
Methods for Activity-Based Memory Maintenance Operations and Memory Devices and Systems Employing the Same
Application:
62/784,085 →
Detection of Illegal Commands
Application:
62/784,927 →
Semiconductor Devices with Package-Level Configurability
Memory Devices, Modules and Systems Having Dynamic Densities
Application:
62/782,276 →
Memory Sub-System with Multiple Ports Having Single Root Virtualization
Application:
62/778,515 →
Multistage Development Workflow for Generating a Custom Instruction Set Reconfigurable Processor
Semiconductor Device Having a Reduced Footprint of Wires Connecting a Dll Circuit with an Input/Output Buffer
Semiconductor Devices Including Insulative Materials Extending Between Conductive Structures
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Jitter Cancellation with Automatic Performance Adjustment
Apparatuses Including Memory Cells with Gaps Comprising Low Dielectric Constant Materials
Apparatuses and Methods Including Memory Access in Cross Point Memory
Apparatuses and Methods to Control Body Potential in 3D Non-Volatile Memory Operations
Memory Including Blocking Dielectric in Etch Stop Tier
Methods for Forming Semiconductor Devices
Methods of Manufacturing a Multi-Device Package
Methods of Fabricating a Decoupling Capacitor in a Semiconductor Structure
Semiconductor Devices
Executing Applications from a Semiconductor Nonvolatile Memory
Application:
16/201,948 →
Publication:
US US20190146812A1
Multi-Partitioning of Memories
Persistent Content in Nonvolatile Memory
Apparatuses and Methods for Sensing a Phase-Change Test Cell and Determining Changes to the Test Cell Resistance Due to Thermal Exposure
Wireless Communication Link Using Near Field Coupling
Memory Device with a Common Source Select Line for Two Memory Portions of a Logic Sector
Programming Non-Volatile Electronic Memory Device with Nand Architecture
Memory Sense Amplifiers and Memory Verification Methods
Memory Systems and Memory Programming Methods
Memory Systems and Memory Programming Methods
Apparatuses and Methods for Coupling Data Lines in Memory Devices
PCT:
PCT/US2018/065554 ↗
Methods of Processing Semiconductor Device Structures and Related Systems
PCT:
PCT/US2018/065693 ↗
Methods of Forming Staircase Structures and Related Staircase Structures and Semiconductor Device Structures
PCT:
PCT/US2018/065638 ↗
Temperature-Based Memory Operations
PCT:
PCT/US2018/063952 ↗
Drift Mitigation with Embedded Refresh
PCT:
PCT/US2018/064928 ↗
Semiconductor Assemblies Using Edge Stacking and Method of Manufacturing the Same
PCT:
PCT/US2018/063657 ↗
Methods Comprising an Atomic Layer Deposition Sequence
PCT:
PCT/US2018/063248 ↗
Polarity-Conditioned Memory Cell Write Operations
PCT:
PCT/US2018/066001 ↗
Semiconductor Devices, and Related Control Logic Assemblies, Control Logic Devices, Electronic Systems, and Methods
PCT:
PCT/US2018/067731 ↗
Hydrosilylation in Semiconductor Processing
PCT:
PCT/US2018/065117 ↗
Sublimation in Forming a Semiconductor
PCT:
PCT/US2018/063555 ↗
Semiconductor Devices Including Control Logic Structures, Electronic Systems, and Related Methods
PCT:
PCT/US2018/067489 ↗
Memory Cells, Memory Arrays, and Methods of Forming Memory Arrays
PCT:
PCT/US2018/064401 ↗
Assemblies Having Conductive Structures Along Pillars of Semiconductor Material, and Methods of Forming Intgrated Circuitry
PCT:
PCT/US2018/062751 ↗
Ufs Based Idle Time Garbage Collection Management
PCT:
PCT/US2018/058197 ↗
Apparatuses and Methods for Sense Line Architectures for Semicondcutor Memories
PCT:
PCT/US2018/066558 ↗
System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network
PCT:
PCT/US2018/058539 ↗
Transistors and Arrays of Elevationally-Extending Strings of Memory Cells
PCT:
PCT/US2018/065462 ↗
Memory Arrays Comprising Memory Cells
PCT:
PCT/US2018/061749 ↗
Methods of Forming a Channel Region of a Transistor and Method Used in Forming a Memory Array
PCT:
PCT/US2018/065437 ↗
Comparing Input Data to Stored Data
PCT:
PCT/US2018/061175 ↗
Ferroelectric Assemblies and Methods of Forming Ferroelectric Assemblies
PCT:
PCT/US2018/063743 ↗
Wave Pipeline
PCT:
PCT/US2018/059540 ↗
Transistors and Methods of Forming Transistors
PCT:
PCT/US2019/012123 ↗
Memory Arrays, and Methods of Forming Memory Arrays
PCT:
PCT/US2018/063978 ↗
Memory Arrays, and Methods of Forming Memory Arrays
PCT:
PCT/US2018/063590 ↗
Transistors Comprising at Least One of Gap, Gan and Gaas
PCT:
PCT/US2018/062475 ↗
Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb, and Capacitor Configurations Incorporating Leaker Devices
PCT:
PCT/US2018/062811 ↗
Multilevel Addressing
PCT:
PCT/US2018/061201 ↗
Data Movement Operations in Non-Volatile Memory
PCT:
PCT/US2018/063570 ↗
Multi-Level Self-Selecting Memory Device
PCT:
PCT/US2018/063309 ↗
Implementing Safety Measures in Applications
PCT:
PCT/US2018/065108 ↗
Methods Used in Forming at Least a Portion of at Least One Conductive Capacitor Electrode of a Capacitor That Comprises a Pair of Conductive Capacitor Electrodes Having a Capacitor Insulator There-Between and Methods of Forming a Capacitor
PCT:
PCT/US2018/065450 ↗
Internal Clock Distortion Calibration Using Dc Component Offset of Clock Signal
PCT:
PCT/US2018/060647 ↗
Recessed Access Devices and Dram Constructions
PCT:
PCT/US2018/065633 ↗
Secure Vehicle Control Unit Update
PCT:
PCT/US2018/065113 ↗
Assemblies Containing Pmos Decks Vertically-Integrated with Nmos Decks, and Methods of Forming Integrated Assemblies
PCT:
PCT/US2018/064411 ↗
Techniques for Precharging a Memory Cell
PCT:
PCT/US2018/064860 ↗
Operations on Memory Cells
PCT:
PCT/US2018/061183 ↗
Techniques to Access a Self-Selecting Memory Device
PCT:
PCT/US2018/063116 ↗
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
PCT:
PCT/US2018/060233 ↗
Using Sacrificial Solids in Semiconductor Processing
PCT:
PCT/US2018/063956 ↗
Freezing a Sacrificial Material in Forming a Semiconductor
PCT:
PCT/US2018/065120 ↗
Managing Partial Superblocks in a Nand Device
PCT:
PCT/US2018/063768 ↗
Common Pool Management
PCT:
PCT/US2018/055005 ↗
Dynamic L2P Cache
PCT:
PCT/US2018/054995 ↗
Interconnect Structures for Preventing Solder Bridging, and Associated Systems and Methods
PCT:
PCT/US2018/056350 ↗
Pillar-Last Methods for Forming Semiconductor Devices
PCT:
PCT/US2018/056355 ↗
Charge Separation for Memory Sensing
PCT:
PCT/US2018/064239 ↗
Secure Message Including a Vehicle Private Key
PCT:
PCT/US2018/063793 ↗
Apparatuses and Methods for Subarray Addressing
PCT:
PCT/US2018/064657 ↗
Apparatuses and Methods for Subrow Addressing
PCT:
PCT/US2018/064658 ↗
Vehicle Secure Messages Based on a Vehicle Private Key
PCT:
PCT/US2018/063810 ↗
Utilizing Write Stream Attributes in Storage Write Commands
PCT:
PCT/US2018/065813 ↗
Variable Modulation Scheme for Memory Device Access or Operation
PCT:
PCT/US2018/050445 ↗
Multiplexing Distinct Signals on a Single Pin of a Memory Device
PCT:
PCT/US2018/052000 ↗
Multiple Concurrent Modulation Schemes in a Memory System
PCT:
PCT/US2018/052006 ↗
Communicating Data with Stacked Memory Dies
PCT:
PCT/US2018/052705 ↗
Memory System That Supports Dual-Mode Modulation
PCT:
PCT/US2018/050434 ↗
Semiconductor Device with a Layered Protection Mechanism and Associated Systems, Devices, and Methods
PCT:
PCT/US2018/063662 ↗
Selectable Trim Settings on a Memory Device
PCT:
PCT/US2018/058852 ↗
Configurable Trim Settings on a Memory Device
PCT:
PCT/US2018/058860 ↗
Trim Setting Determination for a Memory Device
PCT:
PCT/US2018/058876 ↗
Trim Setting Determination on a Memory Device
PCT:
PCT/US2018/058882 ↗
Host Accelerated Operations in Managed Nand Devices
PCT:
PCT/US2018/054981 ↗
Material Implication Operations in Memory
PCT:
PCT/US2018/064656 ↗
Current Separation for Memory Sensing
PCT:
PCT/US2018/064664 ↗
Physical Unclonable Function Using Message Authentication Code
PCT:
PCT/US2018/063143 ↗
Security of User Data Stored in Shared Vehicles
PCT:
PCT/US2018/063641 ↗
Logical Block Mapping Based on an Offset
PCT:
PCT/US2018/063463 ↗
Semiconductor Device Assemblies Including Multiple Stacks of Different Semiconductor Dies
PCT:
PCT/US2018/060234 ↗
Semiconductor Devices Including Control Logic Levels, and Related Memory Devices, Control Logic Assemblies, Electronic Systems, and Methods
PCT:
PCT/US2018/067736 ↗
Certifying Authenticity of Stored Code and Code Updates
PCT:
PCT/US2018/068132 ↗
Performance Level Adjustments in Memory Devices
PCT:
PCT/US2018/064137 ↗
Integrated Assemblies, and Methods of Forming Integrated Assemblies
PCT:
PCT/US2018/060986 ↗
Techniques for Clock Signal Jitter Generation
PCT:
PCT/US2018/061814 ↗
Performance Allocation Among Users for Accessing Non-Volatile Memory Devices
PCT:
PCT/US2019/012067 ↗
Dfe Conditioning for Write Operations of a Memory Device
PCT:
PCT/US2018/055273 ↗
Gap Detection for Consecutive Write Operations of a Memory Device
PCT:
PCT/US2018/055276 ↗
Improved Timing Circuit for Command Path in a Memory Device
PCT:
PCT/US2018/055374 ↗
Write Level Arbiter Circuitry
PCT:
PCT/US2018/053921 ↗
Nand Flash Thermal Alerting
PCT:
PCT/US2018/057556 ↗
Jitter Cancellation with Automatic Performance Adjustment
PCT:
PCT/US2018/066205 ↗
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 27, 2018
From: TUTTLE, JOHN R.
To: KEYSTONE TECHNOLOGY SOLUTIONS, LLC.
Reel/Frame 047595/0667 →
Assignment of Assignor's Interest
Nov 27, 2018
From: KEYSTONE TECHNOLOGY SOLUTIONS, LLC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047650/0192 →
Assignment of Assignor's Interest
Dec 17, 2018
From: PALMER, DAVID A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047793/0747 →
Assignment of Assignor's Interest
Dec 18, 2018
From: HUSH, GLEN E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047811/0239 →
Supplement No. 2 to Patent Security Agreement
Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
Release of Security Interest
Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
Release of Security Interest
Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
Confirmatory License
Oct 23, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065313/0397 →