Time-based access of a memory cell
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
1. An apparatus, comprising:
a memory cell in electronic communication with a digit line;
a sense component coupled to the memory cell, the sense component configured to output a signal that is based at least in part on a duration of time for a voltage level input into the sense component to satisfy a voltage threshold; and
a first latch coupled to the sense component, the first latch configured to output a value of a first signal based at least in part on the signal received from the sense component, wherein the value of the first signal indicates a logic state of the memory cell based at least in part on a duration prior to receiving the signal from the sense component.
2. The apparatus of claim 1 , further comprising:
a controller configured to identify the logic state of the memory cell based at least in part on the value of the first signal when the voltage level input into the sense component satisfies the voltage threshold.
3. The apparatus of claim 1 , wherein the memory cell is configured to store at least three logic states.
4. An apparatus comprising:
a memory cell in electronic communication with a digit line, wherein the memory cell is configured to store at least three logic states;
a sense component coupled to the memory cell, the sense component configured to output a signal that is based at least in part on a duration of time for a voltage level input into the sense component to satisfy a voltage threshold;
a first latch coupled to the sense component, the first latch configured to output a value of a first signal indicative of a logic state of the memory cell based at least in part on the signal received from the sense component; and
a second latch coupled to the sense component, the second latch configured to receive a second signal indicative of a first bit of a logic state identifier associated with the memory cell, wherein the first signal is indicative of a second bit of the logic state identifier.
5. The apparatus of claim 4 , further comprising:
a controller to identify the logic state of the memory cell based at least in part on the first bit and the second bit of the logic state identifier.
6. An apparatus comprising:
a memory cell in electronic communication with a digit line;
a sense component coupled to the memory cell, the sense component configured to output a signal that is based at least in part on a duration of time for a voltage level input into the sense component to satisfy a voltage threshold;
a first latch coupled to the sense component, the first latch configured to output a value of a first signal indicative of a logic state of the memory cell based at least in part on the signal received from the sense component; and
a cascode having a first node coupled to the digit line and a second node coupled to the sense component, the cascode being configured to apply a voltage to the digit line during a read operation.
7. The apparatus of claim 1 , wherein the memory cell comprises:
a ferroelectric capacitor configured to store a polarization state and a dielectric charge state.
8. The apparatus of claim 1 , wherein the sense component in an inverter.
9. The apparatus of claim 1 , wherein the first latch is activated by the signal output from the sense component.
10. An apparatus, comprising:
a sense component coupled to a ferroelectric memory cell;
a first latch coupled to an output of the sense component and configured to output a value of a first time-varying signal based at least in part on receiving a signal indicative of a voltage satisfying a voltage threshold, wherein the value of the first time-varying signal indicates a logic state of the ferroelectric memory cell based at least in part on a duration prior to receiving the signal; and
a controller configured to identify the logic state of the ferroelectric memory cell based at least in part on the value of the first time-varying signal when the voltage into the sense component satisfies the voltage threshold.
11. An apparatus comprising:
a sense component coupled to a ferroelectric memory cell;
a first latch coupled to an output of the sense component and configured to output a value of a first time-varying signal based at least in part on receiving a signal indicative of a voltage satisfying a voltage threshold;
a second latch coupled to the sense component and configured to output a second time-varying signal based at least in part on receiving the signal indicative of the voltage satisfying the voltage threshold; and
a controller configured to identify a logic state of the ferroelectric memory cell based at least in part on the first time-varying signal when the voltage into the sense component satisfies the voltage threshold.
12. The apparatus of claim 11 , wherein the controller is configured to identify the logic state of the ferroelectric memory cell based at least in part on the second time-varying signal.
13. The apparatus of claim 11 , wherein the second latch is configured to receive the signal indicative of the voltage satisfying the voltage threshold.
14. The apparatus of claim 10 , further comprising:
a selection component in electronic communication with an access line, wherein the access line is a plate line or a digit line.
15. The apparatus of claim 10 , wherein the first latch receives the first time-varying signal over an access line.
16. The apparatus of claim 10 , wherein the controller is configured to determine the logic state of the ferroelectric memory cell based at least in part on a duration between beginning to charge the ferroelectric memory cell and receiving the signal indicative of the voltage satisfying the voltage threshold.
17. The apparatus of claim 10 , wherein the controller is configured to determine one bit of data stored on the ferroelectric memory cell using the first time-varying signal.
18. The apparatus of claim 10 , wherein the controller is configured to determine at least two bits of data stored on the ferroelectric memory cell using the first time-varying signal.
19. The apparatus of claim 10 , wherein the controller is configured to determine a mapping between one or more memory states of the ferroelectric memory cell and one or more logic states of the ferroelectric memory cell.
20. An apparatus, comprising:
a sense component coupled to a ferroelectric memory cell;
a first latch coupled to the sense component and configured to output a value of a first time-varying signal based at least in part on receiving a signal from the sense component, wherein the value of the first time-varying signal indicates a logic state of the ferroelectric memory cell based at least in part on a duration prior to receiving the signal;
a second latch coupled to the sense component and configured to output a second time-varying signal based at least in part on receiving the signal from the sense component; and
a controller configured to identify the logic state of the ferroelectric memory cell based at least in part on the value of the first time-varying signal and the second time-varying signal.