Voltage reference computations for memory decision feedback equalizers

1. A device, comprising:

a voltage reference generator configured to produce one or more distortion correction factors; and

a selection circuit configured to:

receive the one or more distortion correction factors from the voltage reference generator;

select a distortion correction factor of the one or more distortion correction factors as a selected distortion correction factor; and

transmit the selected distortion correction factor such that the selected distortion correction factor is used to offset an interference associated with a data stream on a distorted bit.

2. The device of claim 1 , comprising a latching element having a first input configured to be coupled to the selection circuit, wherein the first input is configured to receive the selected distortion correction factor.

3. The device of claim 2 , wherein the latching element is configured to generate a control signal as a binary representation of one or more previous bits of the data stream, and wherein the selection circuit is configured to receive the control signal and select the distortion correction factor based upon the control signal.

4. The device of claim 2 , wherein the latching element comprises a second input configured to receive the distorted bit, wherein the latching element is configured to generate a modified value of the distorted bit based upon the distortion correction factor and the distorted bit.

5. The device of claim 4 , comprising a deserializer coupled to the latching element, wherein the deserializer is configured to receive the modified value of the distorted bit from the latching element and to store an indication of the modified value of the distorted bit.

6. The device of claim 5 , wherein the deserializer is configured to store the indication of the modified value of the distorted bit as a binary representation of one or more previous bits of the data stream.

7. The device of claim 2 , comprising a deserializer coupled to the latching element, wherein the deserializer is configured to generate a control signal as a binary representation of one or more previous bits of the data stream, wherein the selection circuit is configured to receive the control signal and select the distortion correction factor based upon the control signal.

8. The device of claim 1 , wherein the selection circuit comprises a switch configured to selectively transmit the selected distortion correction factor when the switch is activated via a control signal generated based at least in part on one or more previous bits of the data stream.

9. The device of claim 1 , wherein the selection circuit comprises a multiplexer.

10. The device of claim 1 , wherein the distortion correction factors are equal in number to a total number of possible binary states of one or more previous bits of the data stream.

11. The device of claim 10 , wherein the total number of possible binary states of a control signal is dependent upon a number of stored values of the one or more previous bits of the data stream, and wherein the control signal is utilized by the selection circuit to select the selected distortion correction factor.

12. A device, comprising:

a latching element having:

a first input configured to receive a selected distortion correction factor; and

a second input configured to receive a distorted bit, wherein the distorted bit has been distorted based at least in part on an interference associated with one or more previously transmitted bits of a data stream;

a first output configured to transmit a control signal based at least in part on the one or more previously transmitted bits, wherein the control signal is utilized to select the selected distortion correction factor; and

a second output configured to transmit a corrected bit by combining the selected distortion correction factor with the distorted bit.

13. The device of claim 12 , wherein the control signal comprises a binary representation of the one or more previously transmitted bits of the data stream.

14. The device of claim 12 , comprising a selection circuit coupled to the first input and the first output, wherein the selection circuit is configured to:

receive the control signal; and

select the selected distortion correction factor based upon the control signal.

15. The device of claim 12 , comprising a deserializer coupled to the latching element, wherein the deserializer is configured to store an indication of the corrected bit.

16. The device of claim 15 , wherein the deserializer is configured to store the indication of the correct bit as part of a binary representation the one or more previously transmitted bits of the data stream.

17. A method, comprising:

transmitting a selected distortion correction factor to a latching element;

transmitting a distorted bit to the latching element; and

generating, via the latching element, a modified value of the distorted bit based at least in part on the selected distortion correction factor and the distorted bit.

18. The method of claim 17 , wherein the selected distortion correction factor is selected based at least in part on a control signal associated with one or more previously transmitted modified values of distorted bits.

19. The method of claim 18 , comprising transmitting the control signal from the latching element based upon stored indications of values of a set number of the one or more previously transmitted modified values of distorted bits.

20. The method of claim 17 , generating the modified value of the distorted bit as a corrected bit value having compensated for inter-symbol interference due to a predetermined number of one or more previously transmitted modified values of distorted bits.