Error correction code (ECC) operations in memory
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.
1. An apparatus, comprising:
a memory device;
a controller, coupled to the memory device, configured to:
generate a number of low density parity check (LDPC) codewords via a LDPC encoder from user data of a write operation during an encoding operation; and
generate bose-chaudhuri-hocquenghem (BCH) parity bits via a BCH encoder from user data of the write operation during the encoding operation.
2. The apparatus of claim 1 , wherein the user data is split into a number of portions and a number of encoding operations are performed on the number of portions.
3. The apparatus of claim 1 , wherein the number of LDPC codewords generated is 4.
4. The apparatus of claim 1 , wherein an exclusive OR (XOR) operation is executed on the number of LDPC codewords in response to one of the number of LDPC codewords failing an LDPC decoding operation.
5. The apparatus of claim 4 , wherein a BCH codeword is based on a result of the XOR operation.
6. The apparatus of claim 1 , wherein the controller is configured to execute a BCH decoding operation via a BCH decoder using a BCH codeword based on the number of LDPC codewords and BCH parity bits to correct errors associated with an uncorrectable LDPC codeword of the number of LDPC codewords.
7. An apparatus, comprising:
a memory device;
a controller, coupled to the memory device, configured to:
execute a LDPC decoding operation, wherein the decoding operation includes performing a LDPC decoding operation on each of a number of LDPC codewords;
generate a BCH codeword, based on the number of LDPC codewords and a number of BCH parity bits, in response to one of the number of LDPC codewords failing the LDPC decoding operation; and
perform a BCH decoding operation using the BCH codeword to correct errors associated with an uncorrectable LDPC codeword.
8. The apparatus of claim 7 , wherein the LDPC decoding operation includes performing decoding operations on 4 LDPC codewords that are generated.
9. The apparatus of claim 7 , wherein each LDPC codeword of the number of LDPC codewords is 1 KB.
10. The apparatus of claim 7 , wherein the BCH codeword is 1 KB.
11. The apparatus of claim 7 , wherein a success message is sent in response to all of the number of LDPC codewords passing the LDPC decoding operation.
12. The apparatus of claim 7 , wherein the BCH codeword is generated by performing an XOR operation on the number of LDPC codewords.
13. The apparatus of claim 12 , wherein the BCH codeword is generated by concatenating the result of the XOR operation with the number of BCH parity bits.
14. The apparatus of claim 7 , wherein the BCH decoding operation has a correction power of greater than or equal to 8 and less than or equal to 12.
15. A method for performing an error correction code (ECC) operation, comprising:
executing a number of low density parity check (LDPC) decoding operations on a number of LDPC codewords;
executing a bose-chaudhuri-hocquenghem (BCH) decoding operation in response to one of the number of LDPC codewords failing the LDPC decoding operation and a remaining number of the number of LDPC codewords passing the LDPC decoding operation, wherein the BCH decoding operation includes:
generating a BCH codeword based on the number of LDPC codewords and BCH parity bits based on user data of a write operation; and
decoding the BCH codeword using a BCH decoder to correct errors associated with an uncorrectable LDPC codeword.
16. The method of claim 15 , wherein the method includes reducing an overall BCH overhead by 4 times.
17. The method of claim 15 , wherein the BCH decoding operation includes a correction power of ≥8 and ≤12.
18. The method of claim 15 , wherein executing the BCH decoding operation includes using a BCH codeword with at most 14 bits and a number of BCH parity bits that are at most 14 times a correction power of the BCH decoding operation.
19. The method of claim 15 , wherein the method includes the number of LDPC decoding operations being concatenated with a t-correcting BCH decoding operation.
20. The method of claim 19 , wherein concatenating the t-correcting BCH code with the number of LDPC decoding operations, a combined decoding error floor of the number of LDPC decoding operations and BCH decoding operations is reduced.